AI/ML Design Verification Methodology Lead Engineer

Company:
Qualcomm Atheros, Inc.

Job Area:
Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a AI/ML Design Verification Methodology Lead, will involve in developing and implementing verification strategies, methodologies, and environments to ensure the functionality, performance, and robustness of variety of Qualcomm WIFI, connectivity and IOT devices architectures. The successful candidate will also lead a team of verification engineers and collaborate closely with design, architecture, and software teams.

Job Responsibilities

• This role involve defining and driving AI/ML verification methodology, developing and enhancing constrained-random verification environments using SystemVerilog and UVM.
• Leading and mentoring a team of verification engineers, and collaborating cross-functionally with other teams.
• Explore innovative DV methodologies (formal, simulation, and emulation strategies) to continuously push the quality and efficiency of test benches by adopting emerging techniques and tools.
• Act as a technical point of contact to the different IP and SoC design teams
• Provide technical leadership through personal example, mentorship, and strong teamwork

Required Skillset

• Over 5 years of ASIC/SoC verification experience, with at least 2 years in a leadership role.
• Experience with various aspects of digital verification such as test automation, code and functional coverage, constraint randomization, system Verilog assertions, and performance.
• Candidate should have proven experience in verifying complex AI/ML hardware or high-performance compute cores.
• Proficiency in System Verilog / UVM based verification skills, experience with assertions, and coverage-based verification methodology
• Experience with C/C++, assembly language.
• Knowledge of low power design concepts and power management is a big plus.
• Strong communication and leadership skills are also required.
• Experience with AMBA bus protocols
• Experience with GLS, and scripting languages such as Perl, Python is a plus

Minimum Qualifications:
Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Qualifications:
Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
9+ years of ASIC design, verification, validation, integration, or related work experience.
3+ years of experience with architecture and design tools.
3+ years of experience with scripting tools and programming languages.
3+ years of experience with design verification methods.
2+ years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).

Principal Duties and Responsibilities:
Leverages advanced ASIC knowledge and experience to define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power products.
Creates highly advanced architectures, circuit specifications, logic designs, and/or system simulations based on system-level requirements.
Collaborates across functional teams (e.g., software architecture, hardware architecture, product management, program management teams) to develop and execute an implementation strategy that meets system requirements and customer needs.
Evaluates all aspects of highly complex process flow from high-level design to synthesis, place and route, timing and power use, and verification or similarly for custom circuit design/layout flow.
Utilizes tools/applications (e.g., RTL to GDS Flow, Virtuoso) to execute and enable highly advanced architecture and design of multiple complex blocks/SoC or IC Packages.
Writes detailed technical documentation for highly complex EDA/IP/ASIC projects; reviews technical documentation for junior engineers.

Level of Responsibility:
Provides supervision/guidance to other team members.
Decision-making is significant in nature and affects work beyond immediate work group.
Requires verbal and written communication skills to convey complex information. May require negotiation, influence, tact, etc.
Has a moderate amount of influence over key organizational decisions (e.g., is consulted by senior leadership to make key decisions).
Tasks do not have defined steps; planning, problem-solving, and prioritization must occur to complete the tasks effectively.

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Pay range and Other Compensation & Benefits:
$176,300.00 - $264,500.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer - and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.