Job Title : Senior IC Packaging Engineer
Location : San Jose, CA, USA or Atlanta,GA (Hybrid)
Contract: 12+ months
Department: Design
Job Description
Client is seeking a Senior IC Packaging Engineer to provide technical leadership and architectural ownership of advanced IC and System-in-package(SiP) in a fast-growing startup environment. This role is designed for a senior technologist who combines deep hands-on expertise with system-level thinking, and who thrives in high-ambiguity, high-impact settings.
You will define and drive high-performance, low-power packaging architectures spanning 2D and RDL based fan-out (2.5D), chiplet-based designs, and heterogeneous integration, leading efforts from early technology path finding through production ramp. You will work closely with foundries, OSATs, substrate suppliers, and internal cross-functional teams to shape both product execution and long-term packaging strategy.
Key Responsibilities
- Serve as technical authority for IC and SiP packaging across multiple products and programs.
- Own package architecture and technology roadmap, aligned with product, cost, and scalability goals.
- Lead chiplet-based packaging strategies, including UCIe, silicon interposers, and advanced RDL.
- Perform and guide hands-on package design and physical layout, including critical structures for High-speed SerDes/PHY (PCIe, CXL), LPDDR5, UCIe, and Other multi-gigabit interfaces.
- Define substrate stack-ups, materials, bump/RDL architectures, and DFM guidelines for advanced nodes.
- Drive SI/PI, thermal, mechanical, and reliability trade-offs at the system and package levels.
- Lead external engagement with OSATs, foundries, and key suppliers for technology development and manufacturing readiness.
- Influence product roadmap, risk management, and investment decisions through technical insight.
- Establish scalable design methodologies, best practices, and reusable packaging flows.
Qualifications
- BSEE or MSEE (PhD a plus) in Electrical Engineering, or related field.
- Minimum of 10+ years of experience with extensive IC packaging expertise for SoCs, ASICs, or memory products.
- Deep hands-on expertise in Flip-Chip BGA (FCBGA) and System-in-Package (SiP), RDL, silicon interposers, and chiplet architectures (UCIe)
- Strong understanding of electrical, mechanical, thermal, and reliability design trade-offs, Advanced packaging materials and substrate technologies, Design-for-Manufacturing (DFM) and yield optimization
- Demonstrated ability to operate autonomously, make high-impact decisions, and execute in a startup environment.
Required Experience
- Technical leadership of multiple end-to-end packaging programs, from early architecture through high-volume production.
- Proven experience with high-speed SerDes package development, including PCIe Gen5, LPDDR5 / LPDDR5X, USB 3.x or 10G interfaces
- Experience defining die-to-die and chiplet based RDL/bump architecture.
- Direct collaboration with OSATs, foundries, and substrate suppliers for co-development and ramp.
- Strong cross-functional leadership across design, product, test, operations, reliability, and customer teams.
- Clear understanding of cost, yield, schedule, and risk trade-offs at a product and portfolio level.
Tools & Preferred Skills
- Cadence Allegro Package Designer (APD) or equivalent EDA tools.
- Strong background in flip-chip BGA package design and layout.
- SI/PI expertise preferred, including S-parameter extraction and PDN optimization using HFSS, SIwave, or Ansys Designer.
- Experience building new packaging methodologies or platforms from scratch.
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