Design Verification Engineer

Meta Platforms, Inc. (f/k/a Facebook, Inc.) has the following positions in Sunnyvale, CA ASIC Engineer, Design Verification: Develop functional tests based on verification test plan. (ref. code REQ-2512-158352: $186,000/year to $192,170/year) Individual pay is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base salary only, and do not include bonus or equity or sales incentives, if applicable. In addition to base salary, Me

Role: Senior/Staff VLSI Engineer Ethernet FEC DV Duration: 12+ Months Location: San Jose, CA || Onsite Role Job Description-: We are seeking a highly skilled and motivated VLSI Design Verification Engineer with deep expertise in Forward Error Correction (FEC) and Ethernet protocols. In this role, you will own the verification of advanced FEC IP cores (RS-FEC, KR/KP4, or next-gen) within high-speed Ethernet controllers (25G/50G/100G/200G/400G+). You will develop sophisticated UVM environments, d

Role: Design Verification Engineer Location: San Jose CA/ Irvine CA / San Diego CA Job Description:Experience: 6 to 15+ years of experience. Job Requirements are as below: Architect block and full-chip verification environments using HVLs and constrained random techniques for SOCs with embedded CPUs and mixed signal interfaces. Requires UVM, System Verilog, SVA Develop test plans and coverage metrics from specifications and write block and chip-level tests in C,SV,UVM Debug RTL and Gate simula

Location: Sunnyvale, CA Salary: $90.00 USD Hourly - $100.00 USD Hourly Description: Job Title: FPGA Design/Verification Engineer Duration: 6+ Months (Possible Extension) Location: Sunnyvale, CA, Possible: onsite Denver CO. Job Description: The selected candidate will be responsible for ASIC & FPGA verification on R&D program. This engineer will be a verification UVM expert. This engineer with have experience: -Verifying FPGA and/or ASIC designs including creating UVM verification environ