Hi,
Tittle- Physical Design Lead Engineer
Location :: Sunnyvale, CA onsite
Job Type- Fulltime
Must have- Fusion compiler tool knowledge is a requirement for this job.
JD-
What are the top non-negotiable skill sets required for this role?
Strong understanding in the RTL2GDSII flow and design tapeouts in 5nm, 3nm, 2nm process technologies
Experience with low power implementation, power gating, multiple voltage rails, strong UPF/CPF knowledge.
Experience working with most EDA tools like Fusion Compiler/DC/Genus, ICC2/Innovus, Primetime, Redhawk/Voltus, Calibre
Duties:
Develop and own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes.
Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design
Must Have:
10 years of relevant physical design experience
Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low power designs
Knowledge of static timing analysis and concepts, defining timing constraints and exceptions, corners/voltage definitions.
Experience in Block-level and Full-chip floor-planning, power grid planning
Experience with custom or regular clock tree synthesis implementation at block level or top level, and clock power reduction techniques.
Experience with Python, TCL, Perl programming
Nice to Have:
MSEE/CS or equivalent experience.
Best Regards,
Ishika
SR. IT Technical/Engineer Recruiter
Ph No-
Email:
Address: 505 Knolle Court, Saint Augustine, FL 32092
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