FPGA Design Verification Engineer (Only Visa Independent Candidate/W2)

You Are: 

An experienced FPGA Design Verification Engineer able to provide design verification services while working in a fast-paced environment owning DV from TestPlan to TapeOut as working independently demonstrating technical expertise.

 The Work: 

• Extensive experience with FPGA devices and verification
• Testbench development - System Verilog UVM and C tests 

• Integration/development of C tests/APIs and SW build flow 

• Integration/development of UVM mailboxes and HW/SW communication components 

• Test plan development 

• Coverage collection and closure 

• Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope 

• Engage with the team to drive continuous improvement to the verification environment to find more bugs and improve coverage 

• Work as a team to grow together.  

• Mentor and coach junior team members
• Can work independently and demonstrate both breadth and depth of FPGA verification expertise.
• Ability to develop new Universal Verification Components (UVCs), own test plans, and exercise sound judgment on when to escalate issues or seek reviews.

 Here’s what you need: 

A minimum of 5+ years of experience with FPGA Design Verification  

• Bachelor’s Degree or equivalent (12 years) work experience (If an associate’s degree with 6 years of work experience) 

 Bonus points if: 

• SpaceWire Protocol
• DDR4 memory interfaces
• SerDes connectivity
• Configuration, control, and telemetry systems