Design Rule Check(DRC) Engineer

Remote work is Allowed

DRC/LVS Engineer

Role Overview

We seek experienced LVS/DRC engineers to develop high-quality verification decks for our PDK. This contractor position focuses on translating design rules, ground rules, and design manual specifications into robust, coded verification decks. We are looking for seasoned professionals who can take ownership of rule implementation across multiple technologies and process nodes.

The Opportunity

Our current DRC/LVS bandwidth is constrained. Today, a single experienced developer manages multiple technologies, multiple decks, and complex rule sets across our PDK portfolio. We need additional engineering capacity to:

• Develop and optimize DRC decks that translate design rules and ground rules into verification code
• Author LVS decks to ensure layout-to-schematic accuracy and connectivity verification
• Support multiple technology nodes and design kit flavors simultaneously
• Work with design manuals and process specifications to code complex hierarchical and multi-layer rules
• Validate deck quality through rigorous testing and sign-off

This is core PDK development work. We value experienced engineers who can work independently and deliver high-quality verification decks that designers rely on.

Required Experience

• 5+ years of professional DRC and/or LVS deck development
• Proven expertise in translating design manuals and ground rules into verification code
• Strong proficiency in PxL (Synopsys) and/or SVRF (Calibre)
• Hands-on experience developing decks across multiple technologies or process nodes
• Understanding of hierarchical rule structures, multi-layer verification, and deck validation methodology
• Experience working with EDA tools in professional settings; comfort with scripting and automation

Primary Tools & Environment

• Synopsys ICValidator (primary tool for our DRC development)
• Cadence Virtuoso (design and verification platform)
• OPTIONAL: KLayout (for rule checking and mask data analysis)

Required Languages

• PxL (Synopsys) – preferred for our primary development
• Python – for scripting, automation, and deck generation
• OPTIONAL: SVRF (Calibre) – for multi-tool verification and rule translation

Preferred Qualifications

• Experience with SKILL (Cadence) for rule integration and automation
• Proficiency in Siemens (Mentor) Calibre rule development
• Experience developing LVS decks or familiarity with LVS verification methodologies
• Background in advanced technology nodes (FinFET, nanosheet, or below)
• Experience with PDK delivery, design rule documentation, and deck sign-off processes
• Track record of delivering high-quality verification decks that passed design reviews and tapeouts

What You''ll Deliver

• High-quality DRC decks that accurately encode design rules and ground rules
• LVS decks (as applicable) for device and connectivity verification across process nodes
• Well-structured, maintainable verification code in PxL and/or SVRF
• Comprehensive deck documentation and validation reports
• Support for multiple technologies and design kit versions

This is an opportunity to contribute directly to PDK quality and join a team building next-generation semiconductor design infrastructure. We welcome candidates with proven expertise and a commitment to precision in design verification.