Gate-level SigEM/SEB/FIT CAD Engineer

Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it!\\n\\nAs a key member of our best-in-class CAD Group, you will be part of building innovative designs. We will apply your hands-on experience in electromigration (EM), static error band (SEB), failure in time (FIT), self-heating effect (SHE), and thermal analysis to develop, define, and refine the methodologies and flows for gate-level as well as transistor-level designs. Major tasks will include IP / SOC signal EM analysis for clock and data nets, SOC FIT budget validation, power-grid EM verification, 3DIC and interposer thermal integrity, power switch and standard cell EM/SHE characterization, design abstract and reuse, sign-off, and ECO, and much more. Are you ready to join some of the world's leading engineers, and help us deliver the next generation of ground-breaking Apple products?

In this highly visible role, your primary responsibilities will include:\n \tDefine and architect comprehensive EM/SEB/thermal methodologies and drive deployment across multiple advanced node designs with minimal oversight\n \tLead development of customized EM/SEB/thermal solutions which scale with accuracy and capacity challenges, establishing best practices and design guidelines\n \tOwn and drive the entire EM/SEB/thermal flow from concept through sign-off, including automation, quality metrics, and continuous improvement\n \tServe as the technical authority and primary point of contact for various teams (Physical design and Integration, Clock and Signal integrity, Circuit design, Power, Package, System, Technology) on EM/FIT requirements and trade-offs\n \tIndependently develop, validate, and maintain EM/thermal rule decks and verification methodologies for clock trees, high-speed data paths, and critical signal nets across multiple projects\n \tDrive technical engagement with EDA vendors and foundries for tool qualification, model development, enhancement requests, and roadmap alignment\n \tEstablish and lead correlation studies between EM analysis tools and silicon failure analysis data, driving methodology improvements based on findings\n \tMentor entry level engineers on EM/SEB/thermal analysis techniques and best practices

Experience with EM/SEB/FIT/SHE/Thermal methodologies and calculations\nExperience with current density calculations, heating effects, and electromigration failure mechanisms\nExperience in EDA tools and CAD flow development\nMinimum of BS + 10 years of relevant industry experience

Proficiency in at least one of Tcl, Python, and/or Perl scripting languages\nExperience in at least one of the analysis involved in EM - extraction, timing, simulation, EM modeling, physical design, and physical verification\nHands-on knowledge of industry leading EMIR tools e.g. Voltus, Voltus-Fi, RedHawk-SC, Totem\nHands-on experience with analysis, optimization, and debugging of IR/IVD/EM issues on high performance, large-scale designs and silicon\nFamiliarity with advanced packaging technologies (2.5D/3D/3.5DIC) and their unique EM challenges\nExpertise in AI/ML-driven innovation for CAD workflows\nExperience in development of large-scale software in multi-user, multi-site environments\nAbility to coordinate and drive initiatives with little to no oversight\nExcellent communication and presentation skills