ASIC Design and Power Analysis Engineer

Work Location: US - CA Sunnyvale - Hybrid ASIC Power Engineer to perform power analysis and optimizations in ASIC for Meta's AR/VR products. Areas of interests includes Machine Learning. Primary languages are Python, tcl and SystemVerilog. RESPONSIBILITIES Perform PPA optimization with Fusion compiler. Perform RTL and netlist level Power analysis Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction Setup, run, debug and ana

Payrate: $57.00 - $59.00/hr. Responsibilities:Perform comprehensive power analysis at various design stages, spanning from RTL to GDSII.Contribute to the development, improvement, and automation of various power analysis flows. This includes gathering and analyzing large datasets for power modeling via automated processes.Investigate and address power inefficiencies, providing actionable feedback to the RTL design team. Minimum Qualifications:Demonstrated experience with RTL-to-GDSII design flo

ob Title: Senior Verilog Design EngineerJob SummaryWe are looking for a Senior Verilog Design Engineer with 10+ years of experience in RTL design and digital hardware development. The ideal candidate should have strong expertise in ASIC/FPGA design flows, micro-architecture development, and SoC environments, with exposure to PCIe design or verification. Key ResponsibilitiesDevelop and implement RTL using Verilog for ASIC/FPGA platforms. Define micro-architecture and perform RTL coding, simulatio

Location: Gloucester City, NJ Salary: $70.00 USD Hourly - $80.00 USD Hourly Description: Our client is currently seeking a ASIC/FPGA Design Engineer (SMES). Essential Functions: Responsible for deriving engineering specifications from system requirements and developing detailed architecture Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint) Generate test plans Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based