Hiring: DFT Lead | 7nm & Below | Saratoga, CA | Full-Time

Saratoga, CA, US • Posted 12 hours ago • Updated 12 hours ago

Full Time

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We re looking for a seasoned DFT Leader to architect and drive test strategy for complex multi-chip SoCs at advanced nodes (7nm and below).

Own DFT architecture (Scan, LBIST, MBIST, Memory Repair, OCC, ACJTAG/DCJTAG)
Lead ATPG & achieve high @speed scan coverage
Hands-on with Synopsys or Mentor test tools
Multiple deep submicron tape-outs required
SerDes + EMIB exposure is a plus
15+ years semiconductor experience

This is a high-impact leadership role shaping next-gen high-performance silicon.

Interested? Please send me your rsume.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 91010748
Position Id: 8901217
Posted 12 hours ago

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Hiring: DFT Lead | 7nm & Below | Saratoga, CA | Full-Time

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