TITLE:- Sr. Staff Engineer (SystemVerilog & Digital Verification)
LOCATION:- SanJose, CA (onsite)
This role is part of a large RFC/RFIC/DFT engineering organization, focused on advanced digital verification across complex SoC and mixed-signal designs. The engineer will work closely with RTL designers and system architects to define verification strategies and execute block-level and full-chip verification using strict UVM methodology in SystemVerilog.
The scope includes RFID chip verification (with AMCU integration), partial CPU/subsystem verification, high-speed IO and server interconnect verification, GNSS-related blocks, and exposure to mixed-signal and DMS verification. The role requires building UVM environments from scratch, developing constrained-random and directed tests, implementing functional coverage models, and performing deep RTL and protocol-level debugging.
Strong expertise in AMBA protocols (AXI, AHB, APB) and other interfaces (SPI, UART, JTAG, TileLink, custom interconnects) is critical, along with solid CPU/SoC fundamentals, including processor architectures, cache coherency, and memory hierarchy. The engineer will manage regressions, analyze coverage, support low-power verification using UPF, and work with Cadence-based EDA tools (with exposure to VCS/Questa and formal verification as a plus).
The ideal candidate brings 15+ years of hands-on verification experience, a strong debugging and problem-solving mindset, clear technical communication, and the ability to quickly adapt to new methodologies. This is a highly execution-driven, on-site role in San Jose, requiring deep practical expertise rather than purely theoretical knowledge.
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