JOB RESPONSIBILITIES:
• Perform ASIC design implementation in one or more of: logic synthesis, static timing analysis (STA), and place and route (PnR).
• Develop and maintain implementation flows and scripts, and drive timing, power, and area (PPA) closure.
• Perform timing signoff, including constraint (SDC) development and checking, and resolve timing violations.
• Work with RTL design, DFT, and physical design teams to resolve implementation issues.
• Support silicon bring-up and commercialization.
REQUIRED SKILLS:
• BS or BE minimum in Electrical/Computer Engineering or a related field, with 2+ years of ASIC design implementation experience in at least one of STA, synthesis, or PnR
• Hands-on experience with industry-standard EDA tools (for example Synopsys Design Compiler/Fusion Compiler/PrimeTime, or Cadence GenInnovus/Tempus)
• Solid understanding of digital design, timing concepts, and constraints
• Proficiency in scripting (Tcl, Python, Perl, or shell)
• Teamwork, dedication, strong communications and interpersonal skills
• Excellent communication skills both written and verbal
PREFERRED SKILLS:
• Experience implementing high-speed designs, such as SerDes/high-speed PHY or high-frequency digital blocks
• Experience with advanced process nodes, clock tree synthesis, and multi-corner/multi-mode (MCMM) timing closure
• Familiarity with low-power design methodology (UPF) and signoff checks (physical verification, IR/EM)
