Design Verification Engineer

• Posted 3 days ago • Updated 3 days ago
Full Time
On-site
Fitment

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Job Details

Skills

  • Real-time
  • Trading
  • Test Plans
  • Debugging
  • ROOT
  • Collaboration
  • Management
  • Workflow
  • Computer Hardware
  • RTL
  • SystemVerilog
  • UVM
  • Python
  • Linux
  • Electrical Engineering
  • Computer Engineering
  • Computer Science
  • ASIC
  • System On A Chip
  • GPU
  • CPU
  • Artificial Intelligence
  • Machine Learning (ML)
  • Computer Networking
  • FPGA
  • C++
  • Continuous Integration
  • Continuous Delivery
  • Regression Analysis
  • Productivity
  • Recruiting
  • Leadership
  • Integrated Circuit
  • Internal Communications
  • IC
  • People Management

Summary

About the job

Locations: Austin, TX | Chicago, IL | New York, NY | Boulder, CO

We're partnering with a leading technology-driven trading firm that designs high-performance compute platforms used in real-time production environments. Their hardware organization develops custom FPGA and ASIC solutions that directly power low-latency trading systems operating at massive scale.

The team is seeking Design Verification Engineers with strong SystemVerilog/UVM and Python experience who want meaningful ownership over verification methodology, automation, tooling, and infrastructure. You'll work closely with hardware designers to ensure the correctness and robustness of critical systems operating under demanding performance constraints.

This is a highly collaborative engineering environment where verification engineers are given significant ownership over methodology, infrastructure, tooling, and verification strategy rather than simply executing pre-defined test plans. Team members help shape verification frameworks, improve tooling, drive coverage closure, and contribute to the overall development process.

What You'll Do
  • Develop SystemVerilog/UVM testbenches and verification environments
  • Create and execute verification plans for complex RTL designs
  • Drive code and functional coverage analysis and closure
  • Debug and root-cause RTL issues in collaboration with design engineers
  • Develop automation, tooling, and verification infrastructure using Python
  • Manage regressions and CI workflows
  • Improve verification methodologies and overall engineering efficiency
  • Support verification activities across FPGA, ASIC, SoC, networking, and accelerator-based hardware platforms

What We're Looking For
  • 2+ years of professional RTL functional verification experience
  • Strong SystemVerilog experience
  • Strong UVM experience (required)
  • Strong Python programming skills (required)
  • Experience building or maintaining testbenches and verification environments
  • Comfortable working in Linux environments
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
  • Experience with ASIC, SoC, GPU/Graphics, CPU, AI/ML accelerator, networking silicon, or FPGA verification
  • Experience with Verilator and/or Cocotb
  • Experience with C++
  • Experience developing verification frameworks, tooling, or automation
  • Experience with CI/CD, regression infrastructure, or verification productivity improvements

Career Growth

The team is hiring individual contributors ranging from early-career engineers to experienced senior engineers. Candidates with leadership backgrounds are welcome, though this position is currently structured as a hands-on technical IC role rather than a people-management opportunity.

Compensation

Competitive base salary, annual performance bonus, and comprehensive benefits package. Compensation is highly dependent on experience, technical depth, and location.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 90922487
  • Position Id: 24538898
  • Posted 3 days ago
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