Cupertino, California
•
Today
Minimum 6+ years of experience inAnaloglayoutdesign. Experience developing and leading complexlayoutIC for high-speed applications in advanced CMOS FinFET technologies such as 7nm and below at the block level and chip level. Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys. Experience withlayoutof high-performance high-speedanalogmixed-signal blocks such Transceivers, CMOS drivers, high-speed Data converters and PLLs. Experience with floor planning, block level
Easy Apply
Contract, Third Party
Depends on Experience


