Design For Test (DFT) Engineer

Job Description

LeadStack Inc. is an award winning, one of the nation's fastest growing, certified minority owned (MBE) staffing services provider of contingent workforce. As a recognized industry leader in contingent workforce solutions and Certified as a Great Place to Work, we're proud to partner with some of the most admired Fortune 500 brands in the world.


 
Design For Test (DFT) Engineer (W2 only)
Duration:  6+ Months
Location: San Diego, CA – Fully onsite
 
PR: $100/hr - $130/hr
 
Description
The team is looking for a Design-for-Test contractor to test and validate. Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets.
 
JOB RESPONSIBILITIES:
• Experience with memory BIST – Siemens Tessent Flow
• Experience with gate-level simulation and simulation debug
• Experience with automation and scripting – Tcl/Perl/Python
• Experience with scan compression – SEQ/Ultra/TestKompress
• Experience with ATPG – Tetramax
• Experience with ATPG diagnosis, ATE debug and silicon bring up
• DFT pattern translation – VTRAN
• Experience with RTL design – Verilog/system Verilog
• Some experience with STA and timing analysis concepts – PrimeTime (CDC, clock gating checks, timing constraints)
 
Requirements
REQUIRED SKILLS AND EXPERIENCE:
• 5+ years relevant industrial DFT experience
 • Excellent problem solving and debugging skills
 • Ability to complete assignments independently
 
 
 
 
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