ASIC Physical Design Engineer

San Jose, CA, US • Posted 5 hours ago • Updated 5 hours ago
Contract W2
Contract Corp To Corp
On-site
$60 - $65/hr
Fitment

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Job Details

Skills

  • ASIC
  • Data Analysis
  • EMIR
  • Electrical Engineering
  • Electronic Design Automation
  • Information Retrieval
  • Cadence
  • Collaboration
  • Computer Engineering
  • Computer Science
  • DFT
  • Physical Data Model
  • Place And Route
  • Pure Data
  • RTL
  • Scripting
  • Static Timing Analysis
  • EDA
  • Integrated Circuit
  • International Relations
  • Investor Relations
  • LEC
  • Network
  • Synopsys
  • System On A Chip
  • Tcl

Summary

Hiring: ASIC Physical Design Engineer

Location: San Jose, CA(onsite)

Experience: 7 to 12 years

  • This requirement is similar to Physical Design Requirement (PD Engineer).
  • Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.
  • Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.
  • Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence. Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).
  • Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed. Minimum Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.
  • 7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification. Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.
  • Preferred Qualifications: 7+ years of experience in physical design roles and related activities. Proven ability to adhere to tight schedules and implement low-power design techniques.
  • Experience in System-on-Chip (SoC) design and implementation.
  • Expertise in sub-7nm node technologies.
  • Familiarity with industry-standard EDA tools and their capabilities. Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.
  • Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10511336
  • Position Id: 9028148
  • Posted 5 hours ago
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Andrew Fugle

Andrew Fugle

Della Infotech Recruiter @ Della Infotech
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