San Jose, California
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Today
Hiring:ASIC Physical Design EngineerLocation: San Jose, CA(onsite)Experience: 7 to 12 yearsThis requirement is similar to Physical Design Requirement (PD Engineer).Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for your
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Contract, Third Party
$60 - $70


