ASIC Physical Design Engineer

Hiring: ASIC Physical Design Engineer Location: San Jose, CA(onsite) Experience: 7 to 12 years This requirement is similar to Physical Design Requirement (PD Engineer).Job Responsibilities: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals. Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for y

Position:Physical Design Engineer II (eInfochips Inc) Job Description:WhatYou\'llBeDoing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.Partner with the design team to proactively id

Position: Physical Design Engineer II (eInfochips Inc) Job Description: What You'll Be Doing: Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.Partner with the design team to proacti

Physical Design Engineer (PD / PnR / PPA / Timing Closure) Location: Mountain View CA (Onsite) Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floor planning, power planning, placement, clock tree synthesis (CTS), routing, and physical veri