Senior RTL / Static Timing Analysis (STA) Engineer

Location: San Jose, CA (On-site Preferred)
Job Type: Contract
Duration: 12 Months
Experience: 8+ Years Preferred
Pay Rate: $70 per hour

Job Description

We are seeking an experienced Senior RTL / Static Timing Analysis (STA) Engineer with strong hands-on expertise in ASIC RTL design, timing constraint development, Static Timing Analysis, and timing closure.

The ideal candidate will have extensive experience debugging SDC constraints, analyzing timing reports, and working with Synopsys STA and synthesis tools. Experience with DFT timing modes, PCIe timing constraints, and TSMC memory timing constraints is highly desirable. Ideal candidates can email their updated resumes to

Key Responsibilities

• Develop, review, validate, and debug timing constraints for complex ASIC designs.

• Perform Static Timing Analysis (STA) and support timing closure across functional and test modes.

• Develop and debug RTL designs using Verilog/SystemVerilog.

• Analyze SDC constraints, timing exceptions, clock definitions, and timing violations.

• Collaborate with RTL design, verification, synthesis, physical design, and DFT teams to resolve timing issues.

• Debug timing constraints for DFT modes, including scan shift, scan capture, and BIST.

• Utilize Synopsys PrimeTime, Design Compiler, and Fusion Compiler for timing analysis and synthesis.

• Develop automation scripts using Tcl, Perl, Python, or Makefile.

• Support timing constraint verification, design optimization, and ASIC implementation activities.

Required Qualifications

• Bachelor's degree with 8+ years, Master's degree with 6+ years, or PhD with 3+ years of relevant experience.

• Strong hands-on experience in RTL design and Static Timing Analysis (STA).

• Proven experience developing, debugging, and verifying SDC timing constraints.

• Experience with ASIC design flows, timing analysis, and timing closure.

• Understanding of clock domains, setup/hold timing, timing exceptions, and constraint validation.

• Experience with industry-standard STA and synthesis tools.

• Proficiency in at least two scripting technologies: Tcl, Perl, Python, or Makefile.

• Strong debugging, analytical, and cross-functional collaboration skills.

Preferred Qualifications

• 15+ years of ASIC design and timing analysis experience.

• Experience with Synopsys PrimeTime STA, TCM, Fusion Compiler, and Design Compiler.

• Experience analyzing PCIe and TSMC memory timing constraints.

• Knowledge of Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), and Conformal verification.

• Experience with DFT timing closure for scan shift, scan capture, and BIST modes.

• Experience with Synopsys Design Constraints (SDC) debugging.

• Hands-on experience with Tessent and RTL-level DFT insertion.

• Experience supporting complex ASIC and SoC design projects.

Key Technical Skills

RTL Design, Static Timing Analysis, STA, ASIC Design, Verilog, SystemVerilog, SDC, Timing Constraints, Timing Closure, Synopsys PrimeTime, Synopsys TCM, Design Compiler, Fusion Compiler, Tcl, Python, Perl, Makefile, DFT, Scan Shift, Scan Capture, BIST, Tessent, PCIe, TSMC, CDC, RDC, Conformal Verification, ASIC Synthesis, Setup Timing, Hold Timing, Clock Domain Crossing

Ideal Candidate

An experienced ASIC engineer who combines hands-on RTL development with strong STA and timing constraint debugging expertise. Candidates with proven experience using Synopsys tools and resolving complex timing issues across functional and DFT modes will be highly preferred. Send me your updated resume, worth authorization details and other details to