Job Description:
Who You Are
We are seeking a highly motivated senior CPU verification engineer to join our design team. In this role, you will be responsible for driving and executing the functional correctness of CPU logic designs through rigorous pre-silicon verification methodologies. Key Responsibilities:
Senior CPU Verification Engineer
Lead, drive, develop and execute comprehensive verification plans to validate CPU logic against architectural specifications.
Able to build scalable UVM-based testbenches from and define robust functional coverage models.
Run system-level simulations to uncover design bugs and ensure functional integrity.
Debug and root-cause issues in the pre-silicon environment; implement corrective actions to resolve test failures.
Collaborate closely with CPU architects and RTL designers to verify complex architectural and microarchitectural features.
Document verification strategies and lead technical reviews with design and architecture teams.
Maintain and enhance existing verification infrastructure and methodologies.Contribute to the definition and refinement of CPU architecture and microarchitecture features.
Excellent analytical and debugging skills, with a creative approach to problem-solving.
Ability to define and implement validation strategies based on architectural and design insights.
Qualifications:
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must have a Bachelor's Degree in Electrical/Electronic Engineering or Computer Engineering or any STEM related education with at least 4+ years of relevant experience -OR-Master's Degree in Electrical/Electronic Engineering or Computer Engineering or any STEM related education with at least 3+ years of relevant experience.
2+ years of experience in digital logic design, including instruction set execution, ALUs, control units,registers, memory, and system buses.
2+ years of experience in developing UVM-based testbenches for reusable and scalable verification environments.
2+ years of experience in at least one scripting language (e.g., Python, Perl, or Tcl), C++, and SystemVerilog.
Preferred Qualifications
Experience with RTL development
Use of AI agents in Verification
Proficiency with C/C++, System Verilog coding and debug
Knowledge and experience with x86 or any other computer architectures
Familiarity with version control software (GIT).
Experience with Synopsys simulators
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