Technology Lead Memory Team Layout

IC Layout Designer Analog layout, Cadence Virtuoso XL, Calibre, LVS/DRC. Required experience with Global Foundries 55 nm process. Perform block level layout. Work closely with design engineering leads and coordinate assigned projects. Minimum of Associate's degree in IC layout or electronics. Technical focus on analog mask layout with 5 years of experience. Must have experience in Cadence XL environment with a strong debugging background using Calibre physical verification tools. Cadence and Men

Job Title: Senior Software Engineer Linux Kernel & Device Drivers Location: RemoteExperience: 5 to 15 years (depending on grade)job Overview: As a Senior Engineer in the Systems Software team, you will drive the software-hardware co-design for Client AI and data center solutions. This role requires a visionary approach to Linux Kernel Memory Management, specifically focused on heterogeneous memory, virtualization, and high-bandwidth interconnects for our next-generation SoC and SSD platforms. Ke

Location:REMOTEDuration: ~12 months (Immediate start through Q1 next year)Team Size: ~10 Engineers (Mix ofDesign & DV )Question from hiring manager on prior submital: Can you also check with the candidates on their recent hands-on experience with RTL design using SystemVerilog, & working on IPs with multiple clock domains?1. RTLDesignEngineerKey ResponsibilitiesOwn micro-architecture definition from high-level functional specificationsDevelop and implement RTL for complex digital blocksDrive dig

Overview Microsoft's Quantum team is building the first scalable, fault-tolerant quantum computer, advancing everything from quantum hardware and error correction to Azure integration. Our full-stack strategy spans the physics of quantum devices through scalable readout and control infrastructures powered by cryo-electronics. As quantum computing enters a pivotal phase of accelerated growth, this position offers a unique opportunity to contribute meaningfully to a transformative technology, suc