Post Silicon Validation Engineer

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a "CPU Silicon Bring up and Validation Engineer" you would be part of the CPU Silicon Bringup Team, within the CPU team. The charter for CPU Silicon Bringup team would be to prepare for and support bring up of every SoC using the Custom CPUs - from first Silicon through to productization. Roles and Responsibilities: Work with CPU design and verification teams to develop C

Own post-silicon structural test pattern debug and regeneration, including ATPG, MBIST, Boundary Scan, and related DFT flows Analyze pattern failures on silicon and drive corrective actions in collaboration with tester teams Utilize Siemens DFT/ATPG tools to modify, validate, and re-release production-ready test patterns Correlate tester results with design intent to isolate coverage gaps and failure mechanisms Drive closure of post-silicon DFT issues to improve yield and test robustness

.Validate ML-Coprocessor, display SOC, Mixed Signal SOC, and IP. Define validation strategy and test plans for new IP blocks, aligning with RTL, architecture, FW. Develop silicon validation infrastructure and coding C/C++ and Python for emulation (Zebu), FPGA (HAPS), and first silicon platforms. Identify risks and develop mitigation strategies .Execute bring-up/debug, workload enablement, and ML accelerator SW stack validation Perform performance and power characterization under real ML workload