DFT Engineer - Post-Silicon Validation & Pattern Debug (Siemens Tools)

Lead post-silicon debug across functional and stress test modes to root-cause silicon failures Perform shmoo analysis, voltage/frequency margining, and parametric sweeps to identify failure boundaries Debug complex issues involving CDC paths, clocking behavior, resets, and signal integrity Collect, organize, and correlate large silicon datasets to identify systematic failure trends Partner with design, validation, and test teams to drive silicon fixes and workarounds

{"description": "Proto is accelerating the world's transition to an open economy with products that increase access and independence for everyone. We're building Bitkey, a simple and safe self-custody bitcoin wallet that will put customers in control, as well as hardware and software that will help decentralize bitcoin mining and enable new and innovative use cases for bitcoin mining. We're developing these products in the open - you can read more about them at bitkey.build and mining.build . Wi

Role Summary We are seeking a Senior SoC Engineer with strong ARM CPU subsystem experience to serve as the technical bridge between Hardware and Firmware teams. This role focuses on firmware-driven validation, system bring-up, and complex HW-FW debug. Core Responsibilities - Act as the primary interface (POC) for the Firmware team. - Debug firmware-driven issues, including boot failures, system hangs, and performance bottlenecks. - Perform cross-layer debug (RTL/SoC/Firmware) and analyze log

Job Title: Lead ASIC DFT Engineer Location: San Jose, CA - Must Be Able To Go In Office Once Or Twice A Month Duration: Long term Experience Required: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, bo