Physical Design Engineer

About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleetin

FPGA Logic Designer High-Speed SerDes (Hardware Focus) Bay Area, California (On-site/Hybrid) Long-Term Contract Role Overview We are seeking a highly experienced FPGA Logic Designer with deep expertise in high-speed SerDes architectures and PCIe-based designs. This role focuses on hands-on FPGA development, integration of transceivers, and implementing complex high-speed communication protocols in cutting-edge systems. Core Technical Requirements 10+ years of FPGA design experience using Xilinx

Principal RTL Lead High-Speed Ethernet (ASIC)Introduction:We are seeking an experienced Principal RTL Lead to drive the design and verification of next-generation Ethernet subsystems for custom ASIC silicon. This role is central to building architectures that support 400G, 800G, and beyond, enabling ultra-low latency and high reliability in large-scale data centers. As the technical lead, you will guide a team of designers through complex challenges such as multi-lane alignment, Forward Error C

Role: Principal Engineer, RTL Design Location: Mountain View, CA (Onsite) Job Type: Contract Project description The Principal Engineer, RTL Design within the NPU Hardware & Software organization, is a senior individual contributor role for an engineer with deep expertise in RTL design and development for complex digital systems, including neural processing units (NPUs) or similar advanced computing architectures. This role provides expert-level technical leadership across architecture,