ASIC Physical Design Engineer

Job Title: Physical Design Engineer (STA / CTS / Floorplanning) Location: San Jose, CA Experience: 8+ Years Employment Type: Full-Time / Contract Job Description: We are looking for a skilled Physical Design Engineer with strong experience in advanced node physical implementation. The candidate will work on RTL to GDSII implementation, timing closure, and physical verification for complex semiconductor designs. Key Responsibilities: Physical design implementation including Floorplanning, Placem

Job Description Sunnyvale, CA Hybrid RESPONSIBILITIES Perform PPA optimization with Fusion compiler. Perform RTL and netlist level Power analysis Perform post-processing and scripting on report log files for format conversion, data analysis and information extraction Setup, run, debug and analyze reports of ASIC flows (Synthesis, PD, Power, Timing) Implement some blocks at RTL and UPF Ability to document and communicate clearly MINIMUM QUALIFICATIONS 10+ Years of experience as an ASIC Power en

Looking for an Innovative Staff Full-Chip Timing (STA) Engineer - On Site This Jobot Job is hosted by: Lindsey Cusic Are you a fit? Easy Apply now by clicking the "Apply Now" button and sending us your resume. Salary: $175,000 - $235,000 per year A bit about us: We are a growing semiconductor design organization focused on advanced ASIC and SoC development. Our team is built around deep technical expertise, fast execution, and a strong ownership mindset. We work on complex, high-performance

Job Title: DFT Engineer (6+ Years) Location: Santa Clara, California, USA Employment Type: Full-Time Job Summary We are seeking a highly skilled and motivated DFT Engineer with 6+ years of experience to join our team in Santa Clara, CA. The ideal candidate will have strong expertise in Design for Testability (DFT) methodologies, test insertion, and validation for complex SoCs. You will work closely with design, verification, and product engineering teams to ensure high-quality, testable silicon