Hiring: Staff / Sr Staff SoC Clock Design Engineer Saratoga, CA | Full-Time | 7nm & Below

Descriptions & Requirements Job Description and Requirements We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an enthusia

We re looking for a seasoned DFT Leader to architect and drive test strategy for complex multi-chip SoCs at advanced nodes (7nm and below). Own DFT architecture (Scan, LBIST, MBIST, Memory Repair, OCC, ACJTAG/DCJTAG) Lead ATPG & achieve high @speed scan coverage Hands-on with Synopsys or Mentor test tools Multiple deep submicron tape-outs required SerDes + EMIB exposure is a plus 15+ years semiconductor experience This is a high-impact leadership role shaping next-gen high-performance silicon.

Join a cutting-edge hardware company building next-gen silicon powering large-scale AI networking, training & inference. Were looking for a visionary Performance Modeling Leader to define and drive architectural modeling strategy that directly shapes ASIC & SoC design decisions. Lead high-level performance modeling for networking devices Partner with ASIC architects & uArch teams on PPA trade-offs Analyze throughput, latency & bottlenecks to influence architecture Build scalable modeling framew

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: This individual leads, plans, synthesizes ambiguous or conflicting requirements and performs the complex responsibility of the use of EDA tools to execute the architecture and design of an individual block according to design protocol provided. Applies knowledge of memory systems including Cache Controllers, Memory Controller and LPDDR/DDR memory specifications, SRAM archit