Hiring: Staff / Sr Staff SoC Clock Design Engineer Saratoga, CA | Full-Time | 7nm & Below

Saratoga, CA, US • Posted 60+ days ago • Updated 5 days ago
Full Time
On-site
Depends on Experience
Fitment

Dice Job Match Score™

👾 Reticulating splines...

Job Details

Skills

  • circuit design
  • Verilog

Summary

 

Join an innovative hardware company building next-generation silicon to accelerate AI training & inference for large-scale models.

We’re seeking a seasoned Clock Design Lead to define and implement high-speed clock distribution networks for complex, multi-core SoCs at advanced nodes.

Lead SoC clock architecture & timing budgets
Design high-performance, low-skew clock distribution networks
Own CDC strategy, de-skew mechanisms & cross-domain synchronization
Drive clock modeling, STA, SDC/CDC constraints & timing closure
Collaborate with PD on CTS, floorplanning & integration
Multiple 7nm+ tape-outs required
15+ years industry experience

Experience with InnovGenus or Synopsys Fusion Compiler preferred. EMIB exposure is a plus.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 91010748
  • Position Id: 8757950
  • Posted 30+ days ago
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