Hiring: Staff / Sr Staff SoC Clock Design Engineer Saratoga, CA | Full-Time | 7nm & Below

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PD Engineer-Onsite (Manager level) Sunnyvale, CA, USA Fulltime We are looking for a Senior Physical Design Engineer with 814 years of experience to lead and execute RTL to GDSII implementation for low power SoCs on advanced nodes. This role demands deep expertise in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA. What You will Do: Drive physical design flow: synthesis, floorplanning, placement, CTS, routing, timing closure. D

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: This individual leads the team to improve engineering efficiency, product quality and responsibility of working with microarchitecture and RTL design team to implement the designs, meeting aggressive power, area and performance goals using industry standard tools/flows. Works with CPU microarchitecture team to understand specifications and design trade-offs in pipeline and st

Senior Physical Design Engineer Sunnyvale, CA, USA Fulltime Visa- G C and U S C Only We are looking for a Senior Physical Design Engineer with 814 years of experience to lead and execute RTL to GDSII implementation for low power SoCs on advanced nodes. This role demands deep expertise in Synopsys Fusion Compiler, strong scripting and automation, and a proven track record of achieving best-in-class PPA. What You will Do: Drive physical design flow: synthesis, floorplanning, placement, CTS, rout