Staff/Sr Staff SoC Clock Design Engineer opportunity to work for a Hardware company focused on accelerating training and inference performance for large AI models

Full Time opportunity in Saratoga, CA.

Position Overview
We are seeking a highly experienced and motivated Clock Designer Design Lead to drive the definition, architecture, and implementation of high-speed clock distribution networks for complex, large-scale SoC designs. This role is critical in ensuring high-performance, low-skew clocking solutions across multi-core, multi-module systems at advanced process nodes (7nm and below).
Responsibilities

Lead the architecture definition and implementation of high-speed clock distribution networks in large-scale ICs.

Define and manage clock architecture specifications, timing budgets, and design methodologies for SoC designs.

Perform clock distribution design modeling, analysis, and implementation to meet aggressive timing and power targets.

Drive post-silicon clock distribution characterization and debug, identifying performance bottlenecks and optimizing solutions.

Develop cross-clock domain data transfer logic and ensure reliable synchronization across timing domains.

Design and implement de-skew mechanisms and cross-clock domain communication protocols.

Collaborate with physical design teams for optimal clock tree synthesis, floorplanning, and integration into SoC flows.

Own the clocking solution from concept to tape-out, ensuring first-pass silicon success across multiple technology nodes.

Build and evolve clocking design methodologies, ensuring robust, reusable, and scalable design practices.

Support synthesis, STA, and integration teams with design constraints (SDC/CDC) and cross-domain timing closure.

Participate in system-level architecture reviews and cross-functional discussions to drive overall design quality and performance.
Qualifications

15+ years of industry experience in custom circuit design and clock distribution networks for high-speed SoCs.

Demonstrated leadership in delivering complex clock architectures and clock distribution implementations across several tapeouts.

Expertise in clock timing analysis, budgeting, and hands-on experience with clock de-skew and domain crossing techniques.

Proficiency in physical implementation tools such as Cadence InnovGenus or Synopsys Fusion Compiler.

Strong scripting skills in Unix, Perl, Python, or TCL for automation and analysis.

Excellent understanding of synthesis design constraints (SDC, CDC) and their impact on timing and verification.

Preferred Qualifications

Prior experience with EMIB architectures and interconnect bridge designs.

Familiarity with Verilog and SystemVerilog.

Multiple tapeouts in deep submicron nodes (7nm or below).