Job Description
ONSITE in Austin, TX
Must have:
UVM experience
Secondarily:
Cache experience (L1/L2/LLC) and/or Interface experience (AXI/PCI)
Nice to have:
Knowledge of memory subsystem or coherent interconnects is a plus.
Experience with performance-aware verification or performance profiling.
Hardware modeling or emulation experience.
Demonstrated passion for learning modern graphics architectures and evolving GPU technologies.
Description
Help develop comprehensive verification plans, define verification goals, coverage metrics, and sign-off criteria aligned with architectural specifications and integration requirements.
Architect and implement advanced verification environments by designing, developing, and maintaining scalable verification testbenches using SystemVerilog, UVM, and C++, developing test code in parallel with RTL and applying constrained-random testing, coverage-driven verification, and assertion-based techniques to validate complex block and subsystem behaviors.
Support verification methodologies, tools, and automation to improve efficiency and quality across subsystem coverage, while creating targeted and scalable test scenarios that stress interactions across multiple blocks, interfaces, and data paths within the subsystem.
Assist with complex debug and issue resolution by analyzing failures spanning blocks within a subsystem, identifying root causes, and collaborating with design and architecture teams to ensure verification aligns with architectural intent and system-level integration expectations.
Help advance best practices, methodologies by staying ahead of industry trends emerging verification technologies and methodologies.
Requirements
6+ years of experience with a Bachelor's Degree in Computer Science/Engineering, or 4+ years of experience with a Master's Degree, or 2+ years of experience with a Ph.D.
Hands-on experience in GPU, CPU, or advanced semiconductor design verification. Working knowledge of computer architecture and GPU subsystem design, including block-level and subsystem-level integration
Good programming skills in C/C++, Python, Perl, or equivalent.
Familiarity with SystemVerilog and UVM, including constrained-random testing, functional coverage, and assertions.
Knowledge or experience with contributing to verification strategy and execution for multiple subsystem blocks and verification closure across interfaces.
Hands-on experience in debugging, analytical, and problem-solving skills, with proven ability to identify bottlenecks, propose solutions, and execute implementation.
Excellent communication and collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment.Verilog and UVM, including constrained-random testing, functional coverage, and assertions.
Knowledge or experience with contributing to verification strategy and execution for multiple subsystem blocks and verification closure across interfaces.
Hands-on experience in debugging, analytical, and problem-solving skills, with proven ability to identify bottlenecks, propose solutions, and execute implementation.
Excellent communication and collaboration skills, with the ability to navigate ambiguity in a fast-paced, global team environment.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
- Dice Id: wesca004
- Position Id: JOB-5962
- Posted 30+ days ago
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