Apply Now

Principal / Lead Engineer

San Jose, CA, US • Posted 1 hour ago • Updated 1 hour ago

Contract W2

Contract Corp To Corp

On-site

Fitment

Dice Job Match Score™

🔢 Crunching numbers...

Job Details

Skills

Principal / Lead Engineer

Summary

Job Title: Principal / Lead Engineer
Location: San Jose, CA

Job Summary:

We are seeking a highly experienced Principal/Lead Engineer to drive the architecture, development,
integration, and delivery of PCIe Gen5/Gen6 subsystems for next-generation SoCs and chiplet-
based products. The candidate will lead PCIe Controller, PHY and SerDes integration activities,
contribute to Transaction Layer development, and work closely with Architecture, RTL, Verification,
DFT, Physical Design, STA, and Silicon Validation teams.
The ideal candidate should possess deep expertise in PCIe protocol, high-speed interfaces,
subsystem integration, timing closure methodologies, and full ASIC development flow from
architecture through silicon bring-up.

Key Responsibilities:

Lead development and integration of PCIe Gen5/Gen6 Controller, PHY, and SerDes
subsystems.
Define subsystem architecture, interface specifications, microarchitecture, and design
documentation.
Participate in Transaction Layer development and enhancements.
Support PCIe/CXL interoperability and advanced features.
Drive integration of high-speed PHY and SerDes IPs.
Work on:
Link training
Equalization
PLL integration
Reference clock architecture
PIPE interfaces
Lane repair and lane aggregation
Collaborate with analog and PHY teams during integration and debug

Work closely with DV teams to:

Define comprehensive verification plans.
Review UVM-based test environments.
Develop assertions and coverage metrics.
Support protocol compliance testing.
Debug simulation, emulation, FPGA, and post-silicon issues.

Support DFT implementation including:

Scan insertion
MBIST
LBIST
JTAG/Boundary Scan
At-speed testing
Define test requirements for PCIe controller and PHY subsystems.
Collaborate with DFT and silicon validation teams to achieve coverage target
Develop and maintain subsystem-level SDC constraints for:
Synthesis
Static Timing Analysis
Place & Route
Timing signoff
Work with PD and STA teams to achieve timing closure.
Silicon Bring-Up & Debug

Support:

PCIe link training debug
Compliance testing
Silicon characterization
Performance tuning
Analyze protocol traces and lab debug logs.

Education:

B.E./B.Tech/M.E./M.Tech in Electronics, Electrical Engineering, Computer Engineering, or
related discipline. With 10+ years of experience
Masters degree preferred for Principal Engineer role.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 10106248
Position Id: 2026-4412
Posted 1 hour ago

Create job alert

Never miss an opportunity! Create an alert based on the job you applied for.

Similar Jobs

Principal / Lead Engineer

San Jose, California

•

5d ago

Role:Principal / Lead Engineer Location: San Jose, CA Let's create our future together at The AES Group! About The AES Group The AES Group is a premier technology and engineering consulting company that has been bringing businesses and talent together for over 20 years to deliver innovative solutions that make a positive impact. We help organizations modernize their technology through cloud, data, AI, engineering, cybersecurity, and emerging technologies. Job Summary: We are seekin

Easy Apply

Contract, Third Party

Depends on Experience

Lead Engineer PCIe Gen5/Gen6 Controller, PHY & SerDes Integration

San Jose, California

•

Yesterday

Job Title: Lead Engineer PCIe Gen5/Gen6 Controller, PHY & SerDes Integration Location :San Jose, CA - Relocation is Fine MST AND PST Job Summary We are seeking a highly experienced Principal/Lead Engineer to drive the architecture, development, integration, and delivery of PCIe Gen5/Gen6 subsystems for next-generation SoCs and chiplet-based products. The candidate will lead PCIe Controller, PHY and SerDes integration activities, contribute to Transaction Layer development, and work closely with

Easy Apply

Third Party, Contract

Up to $60

Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

San Jose, California

•

Yesterday

Position Summary Seeking a Principal Verification Engineer to lead endtoend verification of PCIe Gen5/Gen6 subsystems, including Transaction Layer, Controller, PHY, and SerDes. This role owns verification strategy, UVM environment architecture, coverage closure, protocol compliance, and leadership of a verification team. Requires deep expertise in PCIe protocol, LTSSM, PHY/SerDes interactions, UVM, assertions, formal verification, emulation, and postsilicon debug. Main Skills (Core Requirements)

Easy Apply

Contract, Third Party

Up to $60

Lead Verification Engineer / Principal Verification Engineer – PCIe Gen5/Gen6

San Jose, California

•

Today

Job Title: Lead Verification Engineer / Principal Verification Engineer PCIe Gen5/Gen6 Location: San Jose, CA Experience: 10+ years Position Summary We are seeking a highly experienced Verification Lead to own the end-to-end verification of PCIe Gen5/Gen6 subsystem with Transaction Layer, Controller, PHY and Serdes. The candidate will be responsible for verification planning, methodology definition, UVM environment architecture, coverage closure, protocol compliance verification, and leadershi

Easy Apply

Contract, Third Party

55 - 60

Search all similar jobs

More jobs at AIT Global, Inc. in San Jose, CA