Design For Test (DFT) Engineer

5+ years of SoC-level front-end integration experienceStrong background in multi-IP subsystem assembly and third-party IP integrationExperience configuring and integrating NoC / interconnect fabricsGeneral DFT awareness at the SoC integration levelComfortable working cross-functionally with verification, physical design, and DFT teamsProficiency in Verilog / SystemVerilog

5+ years of digital front-end / RTL design experienceExperience integrating CPU cores, bus architectures, and peripheral IPs into SoC or ASIC designsWorking knowledge of ARM AMBA protocols AXI / AHB / APB(Assumption: viewed as a strong plus please let me know if this should be mandatory) Strong subsystem-level integration and debug skillsProficiency in Verilog / SystemVerilog

5+ years of digital front-end / RTL design experienceExperience integrating CPU cores, bus architectures, and peripheral IPs into SoC or ASIC designsWorking knowledge of ARM AMBA protocols AXI / AHB / APB(Assumption: viewed as a strong plus please let me know if this should be mandatory) Strong subsystem-level integration and debug skillsProficiency in Verilog / SystemVerilog

RequirementsKnowledge of semiconductor ASIC design/verification methodologies and flows Working knowledge of Verilog/SystemVerilog/UVM Strong programming skills including object-oriented programming Working experience with digital logic design and verification Practical experience in D2D, NOC, AXI, Ethernet, DDR/LPDDR, HBM, Security, Networking, ARM CPU subsystems Demonstrates good analysis, problem-solving, and critical thinking skills Effective interpersonal, teamwork, and communication skills