Physical Design Engineer :: San Jose, CA (onsite) :: Long Term Contact

San Jose, CA, US • Posted 11 hours ago • Updated 46 minutes ago
Contract W2
Contract Corp To Corp
On-site
Fitment

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Job Details

Skills

  • Debug
  • Cadence
  • Physical Design
  • Analog Silicon

Summary

Physical Design Engineer

San Jose, CA (onsite)

Long Term Contact

  • Strong experience in RTL synthesis using Cadence GenFusion compiler, including SDC constraint development and QoR optimization (timing, area, power)
  • Hands-on expertise in Static Timing Analysis using Tempus, including setup/hold closure, MMMC scenarios, OCV, and timing signoff concepts
  • Ability to analyze and debug timing violations across synthesis and floorplan stages and drive closure
  • Experience in block-level floorplanning using Cadence Innovus, or fusion compiler including macro placement, IO planning, utilization,
  • Experience in advanced nodes (5nm or below) with ability to work in a fast-paced, execution-driven environment (onsite 5 days/week mandatory)
  • Foundry is a plus
  • Atleast 8 Years of experience
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 90719156
  • Position Id: 2026-11824
  • Posted 11 hours ago
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