Physical Design Engineer - San Jose, CA – Onsite - Contract role

Physical Design Engineer San Jose, CA (onsite) Long Term Contact Strong experience in RTL synthesis using Cadence GenFusion compiler, including SDC constraint development and QoR optimization (timing, area, power) Hands-on expertise in Static Timing Analysis using Tempus, including setup/hold closure, C scenarios, OCV, and timing signoff concepts Ability to analyze and debug timing violations across synthesis and floorplan stages and drive closure Experience in block-level floorplanning using Ca

Position: Physical Design Engineer / Staff Engineer Location:San Jose CA Contract More than 12 months Relocation consultants are also considerable.. Job Responsibilities: We are seeking experienced Physical Design Engineers with expertise in top-level signoff for complex SoCs on advanced nodes (7nm/5nm/3nm). Candidates should have multiple full-cycle tapeouts and strong experience in signoff-to-tapeout closure. Key Responsibilities: Drive full-chip/top-level signoff activities Collaborate with

Title: ASIC RTL Design Engineer - Onsite Mandatory skills: SoC Architecture, ASIC design flow, RTL coding, debugging, verification, supporting synthesis, timing closure, ARM cores, I/O standard interfaces, Ethernet, DDR, DMA, PCIE, SATA, internal IPs, digital CMOS processes, SoC design, Chip definition, Architecture development, modeling, micro-architectural specifications, micro-architectural specifications, logic implementation, emulation, debug Description: JOB DUTIES: The work will expose th

In-Person Interview Required! SoC RTL Design Engineer San Jose, CA: 100% Onsite 6 + Months $60-$62.50/HR Role: Design and develop advanced SoCs across architecture, RTL, and verification. Responsibilities: RTL design, verification, and debugging Support synthesis and timing closure Work with ARM cores, DDR, PCIe, Ethernet, and IP Collaborate with design and bring-up teams Qualifications: Experience in ASIC/SoC design and RTL coding Knowledge of ARM and standard I/O interfaces Dexian stands a