Design Engineer

This is Ganesh from DELLA INFOTECH INC. We have an outstanding opening for you for the opportunity below. Please check the job description and share your updated resume, if you are interested. Hiring: Senior ASIC RTL-to-Physical Design (RTL2PD) / RTL Synthesis Engineer Location: San Jose, CA(onsite) Experience: 8 to 12 years What will Be Doing: RTL Synthesis, Constraint writing, validation, Static timing AnalysisWriting Scripts/Modiying scripts for RTL synthesis, SDC creation, STADebug synthesi

This position is for a Physical Design Engineer based in Sunnyvale, CA. The successful candidate will be responsible for driving RTL synthesis and optimization to achieve performance, power, and area goals for complex ASIC/SoC designs. They will work closely with various teams to ensure optimal timing, congestion, and power distribution in the design. ResponsibilitiesDrive RTL synthesis and optimization to achieve performance, power, and area (PPA) goalsPerform floorplanning for complex ASIC/SoC

Position: Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position Overview We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering

Job Details: Job Description: Altera is a leader in FPGA innovation, delivering programmable solutions that power AI, cloud computing, networking, and edge applications. Our FPGA compiler and development tools are central to enabling customers to efficiently design, optimize, and deploy complex hardware systems on advanced FPGA platforms. Position Overview Altera is seeking a FPGA Development Tools Engineer to join our Synthesis team, focused on advancing the next generation of FPGA compilat