DFT Engineer (Only W2)

Job Title: SLT Engineering Technician-QC:JC# R-183727 Work Setup:Onsite Compensation:$70K$75K + benefits Employment Type:Full-time (Regular) Location:Santa Clara, CA Position Summary The SLT Engineering Technician supports engineering activities related to system-level testing, hardware checkout, program validation, sample processing, and engineering experiments utilizing SLT systems. This position works from written and verbal instructions to support testing, collect engineering data, troublesh

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing closure

Salary: 100K+ benefitsFulltime onlyLocation- Santa Clara 100% on-siteExp- 3yrs-15yrs Post Silicon Validation Engineering BS Degree in EE with one or two years of experienceKnowledge of board bring up,HW troubleshooting skillsand board testing as per the test planFamiliarity of working in lab environment inelectrical measurements of different IO interfaces(PCIE, USB, HMDI and I2C/SPI)and using Test Equipment like Oscilloscope, DAQ, Multi-meter, Power Supply and Logic analyserAbility to read sche

Customer:MetaLocation:Sunnyvale, CAHybrid work 2 to 3 days a weekJC:184527Salary: 5 to 10 years - 140K; 10+ yrs - 160K maxFirmware Engineer Post-Silicon ValidationJob SummaryWe are seeking a Firmware Engineer to join the Reality Labs Silicon Validation team. In this role, you will develop, debug, and maintain embedded firmware that enables post-silicon bring-up, validation, and characterization of next-generation silicon platforms. You will work closely with silicon validation, hardware, ASIC,