Gate-level SigEM/SEB/FIT CAD Engineer

Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it!\\n\\nAs a key member of our best-in-class CAD Group, you will be part of building innovative designs. We will apply your hands-on experience in electromigration (EM), static error band (SEB), failure in time (FIT), self-heating effect (SHE), and thermal analysis to develop, define, and refine the methodologies and flows for gate-level as well as transistor-level designs. Major tasks will include IP / SOC signal EM analysis for clock and data nets, SOC FIT budget validation, power-grid EM verification, 3DIC and interposer thermal integrity, power switch and standard cell EM/SHE characterization, design abstract and reuse, sign-off, and ECO, and much more. Are you ready to join some of the world's leading engineers, and help us deliver the next generation of ground-breaking Apple products?

In this highly visible role, your primary responsibilities will include:\n \tContribute to the development and deployment of comprehensive EM/SEB/thermal methodologies across multiple advanced node designs \n \tDevelop and implement customized EM/SEB/thermal solutions which scale with accuracy and capacity challenges, following established best practices and design guidelines\n \tSupport and maintain the EM/SEB/thermal flow from concept through sign-off, including automation, quality metrics, and continuous improvement\n \tCollaborate with and support various teams (Physical design and Integration, Clock and Signal integrity, Circuit design, Power, Package, System, Technology) on EM/FIT requirements and trade-offs\n \tDevelop, validate, and maintain EM/thermal rule decks and verification methodologies for clock trees, high-speed data paths, and critical signal nets across multiple projects\n \tWork closely with EDA vendors and foundries for tool qualification, model development, enhancement requests, and roadmap alignment\n \tParticipate in correlation studies between EM analysis tools and silicon failure analysis data, contributing to methodology improvements based on findings

Experience with EM/SEB/FIT/SHE/Thermal methodologies and calculations\nMinimum BS + 3 years of relevant industry experience

Understanding of current density calculations, heating effects, and electromigration failure mechanisms\nExperience in some of the analysis involved in EM - extraction, timing, simulation, EM modeling, physical design, and physical verification\nExperience in EDA tools and CAD flow development\nProficiency in at least one of Tcl, Python, or Perl scripting languages\nExposure to or knowledge of industry leading EMIR tools e.g. Voltus, Voltus-Fi, RedHawk-SC, Totem\nExperience with analysis, optimization, or debugging of IR/IVD/EM issues on high performance, large-scale designs and silicon\nFamiliarity with advanced packaging technologies (2.5D/3D/3.5DIC) and their unique EM challenges\nInterest in AI/ML-driven innovation for CAD workflows\nExperience in development of software in multi-user, multi-site environments\nAbility to coordinate and drive initiatives with appropriate guidance\nStrong communication and presentation skills