Design Verification Engineer

Sunnyvale, CA, US • Posted 60+ days ago • Updated 11 days ago
Full Time
On-site
Depends on Experience
Fitment

Dice Job Match Score™

⭐ Evaluating experience...

Job Details

Skills

  • AXI
  • DDR SDRAM
  • Ethernet
  • SystemVerilog
  • Testing
  • UVM

Summary

Hi,

Full Time / Permanent Role

Role: Design Verification Engineer

Location : Sunnyvale CA / Austin TX

Candidates with AXI and PCIE or Ethernet or DDR experience. Scripting is a plus

Strong understanding of SV and UVM and good debugging skills.

Build UVM/System Verilog-based verification environments for IP/subsystem/SoC level testing

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 10121364
  • Position Id: 8861636
  • Posted 30+ days ago
Contact the job poster
AP

Arun Prasath

Recruiter @ Reveille Technologies
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