PCIe Verification Engineer

San Jose, CA, US • Posted 7 hours ago • Updated 7 hours ago
Contract W2
No Travel Required
Able to Sponsor
On-site
Depends on Experience
Fitment

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Job Details

Skills

  • Code Coverage
  • Computer Engineering
  • Debugging
  • Computer Hardware
  • Electrical Engineering
  • Emulation
  • PCI Express
  • Payment Card Industry
  • Physical Layer
  • Electronics
  • Regulatory Compliance
  • Strategic Planning
  • SystemVerilog
  • Training
  • Veritas Cluster Server
  • Switches
  • Signal Integrity
  • SERDES
  • RTL
  • UVM
  • Testing

Summary

PCIe Verification Engineer 

Location: San Jose, CA Or Silver Lake, CO ( Day One Onsite)
Job Description:

Experience: 7+ Years Education: Bachelor/Master of Engineering (B.E./B.Tech/MS) in Electronics, Electrical, Computer Engineering, or a related field

Role Summary:

Drive the pre-silicon verification of next-generation PCIe Switch and Retimer designs across Gen4, Gen5, and Gen6 specifications. Utilizing SystemVerilog and UVM, you will ensure robust protocol compliance, high-performance throughput, and seamless interoperability for cutting-edge silicon.

Key Responsibilities:

  • Strategic Planning: Architect and execute comprehensive PCIe verification plans to ensure full specification coverage.

  • Environment Development: Build and maintain sophisticated, UVM-based verification environments from the ground up.

  • Protocol Deep-Dive: Verify intricate PCIe protocol behaviors, including LTSSM transitions, link training flows, and complex error handling mechanisms.

  • Feature Validation: Validate specialized Switch and Retimer features alongside cross-vendor interoperability.

  • RTL Debugging: Perform rigorous debug of RTL and protocol-level issues while conducting detailed functional and code coverage analysis.

Required Skills:

  • Protocol Expertise: Strong command of PCIe protocols, specifically Gen4 and Gen5, with Gen6 knowledge considered a significant advantage.

  • Methodology: Advanced proficiency in SystemVerilog, UVM, and the implementation of functional assertions.

  • Tooling: Extensive experience navigating industry-standard simulators such as VCS, Questa, or Xcelium.

Nice to Have: 

  • Compliance & Physical Layer: Familiarity with PCI-SIG compliance testing, SerDes/Signal Integrity (SI) fundamentals, and hardware emulation environments.

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 91126058
  • Position Id: 8924729
  • Posted 7 hours ago
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