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Role : Lead ASIC DFT Engineer
Location : San Jose, CA (Remote)
Duration : 12 Months
Job Description:
Experience Required:
10+ years of hands-on experience in ASIC Design-for-Test (DFT)
Role Summary:
We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.
Key Skills Required:
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•
8d ago
5+ years of SoC-level front-end integration experience Strong background in multi-IP subsystem assembly and third-party IP integrationExperience configuring and integrating NoC / interconnect fabricsGeneral DFT awareness at the SoC integration levelComfortable working cross-functionally with verification, physical design, and DFT teamsProficiency in Verilog / SystemVerilog
Easy Apply
Contract, Third Party
Depends on Experience
Remote
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Today
12+ month contractRemote/3 Main priorities below: 1- Tile Based Approach 2-Tessent SSN- specifically SSN 3- MCM Packages/Die-To-Die Chips DFT engineer- Expert with Tessent tools. Experience with Tessent SSN. Experience working on ATPG, MBIST, JTAG, DFT Insertion. Experience with own DFT Verification. Experience with ICL PDL.
Easy Apply
Contract
60 - 90
Remote
•
8d ago
5+ years of SoC-level front-end integration experienceStrong background in multi-IP subsystem assembly and third-party IP integrationExperience configuring and integrating NoC / interconnect fabricsGeneral DFT awareness at the SoC integration levelComfortable working cross-functionally with verification, physical design, and DFT teamsProficiency in Verilog / SystemVerilog
Easy Apply
Contract, Third Party
Depends on Experience
Remote
•
Yesterday
Role: Digital Front-End Engineer CPU / BUS / Peripheral Integration Location: Remote 5+ years of digital front-end / RTL design experienceExperience integrating CPU cores, bus architectures, and peripheral IPs into SoC or ASIC designsWorking knowledge of ARM AMBA protocols AXI / AHB / APB(Assumption: viewed as a strong plus please let me know if this should be mandatory)Strong subsystem-level integration and debug skillsProficiency in Verilog / SystemVerilog Role: Digital Front-End Engineer DSP
Easy Apply
Contract
$40 - $50
