Physical Design with - Genus & Innovus || FTE/W2 || California - onsite

Santa Clarita, CA, US • Posted 1 day ago • Updated 1 day ago
Full Time
24 Months
On-site
Fitment

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Job Details

Skills

  • RTL
  • Physical Design
  • ASIC
  • Cadence
  • Genus
  • Innovus
  • PrimeTime
  • Tempus
  • Calibre

Summary

Hi,
Please check the below position Job Title: Physical Design (PD) Engineer Genus & Innovus
Location: California (Onsite/Hybrid)
Employment Type: Contract/ Full-Time
Any visa

Job Description

We are seeking an experienced Physical Design (PD) Engineer with 6+ years of ASIC Physical Design experience. The ideal candidate should have strong expertise in Cadence Genus and Innovus and hands-on experience in the complete physical design flow from synthesis through signoff. The candidate will work closely with RTL, DFT, STA, and backend teams to deliver high-performance, low-power, and timing-closed designs. Key Responsibilities
  • Execute end-to-end ASIC Physical Design flow including synthesis, floorplanning, placement, CTS, routing, optimization, and physical verification.
  • Perform RTL-to-GDSII implementation using Cadence Genus and Cadence Innovus.
  • Develop and optimize floorplans considering power, performance, and area (PPA).
  • Perform placement optimization, clock tree synthesis (CTS), routing, and congestion analysis.
  • Close timing by resolving setup, hold, transition, and capacitance violations.
  • Perform power optimization and IR drop analysis.
  • Collaborate with RTL, DFT, STA, and verification teams to resolve implementation issues.
  • Conduct physical verification including DRC, LVS, and antenna checks.
  • Analyze and resolve signal integrity, electromigration (EM), and reliability issues.
  • Support ECO implementation and timing closure activities.
  • Develop and maintain backend automation scripts using Tcl, Perl, or Python.
  • Participate in design reviews and contribute to methodology improvements.
Required Skills
  • 6+ years of experience in ASIC Physical Design.
  • Strong hands-on experience with Cadence Genus and Cadence Innovus.
  • Solid understanding of the complete ASIC implementation flow.
  • Experience with floorplanning, placement, CTS, routing, timing closure, and ECO implementation.
  • Strong knowledge of Static Timing Analysis (STA) concepts.
  • Experience with timing constraints (SDC), MMMC setup, and timing optimization.
  • Understanding of physical verification (DRC/LVS) and signoff methodologies.
  • Familiarity with low-power design techniques and UPF/CPF.
  • Experience with IR drop, EM, signal integrity, and power analysis.
  • Proficiency in Linux/Unix environments.
  • Strong scripting skills in Tcl, Perl, or Python.
  • Excellent debugging, analytical, and problem-solving skills.
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: 91126316
  • Position Id: 2026-23639/4750
  • Posted 1 day ago
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