Senior FPGA Design and Validation Engineer

Please note this is a 5-6 months contract position. This position is onsite in Santa Clara, CA. Client is looking for Design and Developer skills. Required Skills and Experience 4+ years of hands-on FPGA design and development experienceStrong understanding of digital logic, timing analysis, and debuggingProficiency in Verilog/SystemVerilogExperience with FPGA toolchains such as Xilinx Vivado, Lattice Diamond, or equivalentBachelor's degree in Mechanical Engineering, Electrical Engineering, or a

General Skills: Expert communicator across global, cross-cultural, and cross-functional teams. Strong analytical, system level, and architectural thinking. Proven ability to lead technical initiatives without direct authority. High bar for design correctness, validation, and quality. Collaborative mindset across hardware, software, and verification organizations. Required Specialized Skills: Extensive experience in RTL design using Verilog/SystemVerilog for complex digital systems, preferably NP

Role: Principal Engineer, RTL Design Location: Mountain View, CA (Onsite) Job Type: Contract Project description The Principal Engineer, RTL Design within the NPU Hardware & Software organization, is a senior individual contributor role for an engineer with deep expertise in RTL design and development for complex digital systems, including neural processing units (NPUs) or similar advanced computing architectures. This role provides expert-level technical leadership across architecture,

Hi, our client is looking for a FPGA Verification Engineer. Role:: FPGA Verification Engineer Location: Mountain View, CA Visa: Any valid working visa Type: Hybrid Job Description Strong understanding of FPGA design principles and architectures. Proficiency in System Verilog and UVM verification methodology. Experience with industry-standard verification tools (e.g., QuestaSim, Synopsys VCS). Knowledge of code coverage and functional coverage analysis. Excellent debugging and problem-solving