Design Verification Engineer (Santa Clara, CA / Austin, TX / Boston, MA)

Austin, TX, US • Posted 1 day ago • Updated 1 day ago

Contract W2

Contract Corp To Corp

No Travel Required

On-site

$50 - $55/hr

Fitment

Dice Job Match Score™

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Job Details

Skills

SystemVerilog
RTL design
Data Fabric
Perl
Ruby
Make
UVM

Summary

Onsite Position

Preferred Experience:

Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or similar tools
Exposure to RTL design, software development, formal verification, or other related domains
Good understanding of computer organization / architecture
Experience or familiarity with formal tools and/or functional verification tools from VCS, Cadence, Mentor Graphics

Key Responsibilities:

Write tests, sequences, and testbench components in SystemVerilog and UVM, along with formal methods to achieve verification of the design
Coordinate with RTL engineers to implement logic design for better clock gating and verify various aspects of the design
Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture
Collaborate with architects, hardware engineers, and multiple IP development groups
Drive formal verification for the block and write formal properties and assertions to verify the design
Responsible for verification quality metrics such as pass rates, code coverage, and functional coverage

Academic Credentials:

Bachelor s or Master s degree in Computer Engineering / Electrical Engineering preferred

Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.

Dice Id: 91135976
Position Id: 8920243
Posted 1 day ago

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