Design Verification Engineer

Onsite Position Preferred Experience: Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or similar toolsExposure to RTL design, software development, formal verification, or other related domainsGood understanding of computer organization / architectureExperience or familiarity with formal tools and/or functional verification tools from VCS, Cadence, Mentor GraphicsKey Responsibilities: Write tests, sequences, and testbench

Xoriant is an equal opportunity employer. No person shall be excluded from consideration for employment because of race, ethnicity, religion, caste, gender, gender identity, sexual orientation, marital status, national origin, age, disability or veteran status. TITLE:- Front-End Infrastructure Engineer (RTL/Design Verification) LOCATION Austin , TX (Onsite) DURATION 6+ Months (May get extend) MODE OF INTERVIEW onsite RATE As per market (Only Xoriant W2 , no Vendor Employees) JOB DESCRIPTION The

Design Verification (DV) Engineer Key Responsibilities Develop and maintain UVM-based SystemVerilog testbenchesCreate reusable verification components and environmentsDevelop and execute verification plans for subsystem and block levelDebug RTL issues and collaborate closely with designContribute to end-to-end validation flowsDrive coverage closureRequired Qualifications Strong hands-on expertise in UVM and SystemVerilogExperience with ARM-based protocols including:APBAXI (no CHI/coherency requi

Position: Data Fabric Verification Engineer ( 20 Positions) Location: Austin, TX, Santa Clara, CA or Boston, MA (Onsite) Duration: 6 Months+ Job Description: Data Fabric verification engineer: 5 to 20 years of experience PREFERRED EXPERIENCE: Architected and developed complex verification environments in SystemVerilog, including scripting using Perl, Ruby, Make, or the likes.Exposure to RTL design, software development, formal verification, or other related domains.Good understanding of compu