Design Verification Engineer (GPU)

San Jose, CA, US • Posted 30+ days ago • Updated 5 days ago
Contract W2
Occasional Travel Required
On-site
Depends on Experience
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Fitment

Dice Job Match Score™

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Job Details

Skills

  • C++
  • CPU
  • GPU
  • Python
  • Open Verification Methodology
  • Debugging
  • SystemVerilog
  • UVM

Summary

Job Title: "Design Verification Engineer (GPU)"

Location: San Jose, CA (Onsite, 5 days a week)

Duration: Long Term

Description

As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date IEEE UVM version will place you among the elite within our profession.

Role and Responsibilities: Key responsibilities include

  • Work with architects and designers to build verification environments and test plans
  • Craft functional verification coverage strategy to ensure complete test suite implementation
  • Develop assertions and checks to optimize isolation time and produce meaningful failing signatures
  • Analyze failing tests to root cause along, working with RTL and reference modeling teams
  • Provide input on Architectural and Micro-Architectural specifications for testability and accuracy
  • Examine code coverage results, identifying exclusions and improving stimulus
  • Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics

Skills and Qualifications: Minimum requirements:

  • BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role
  • Proficient in System Verilog/UVM/OVM, and OOP/C++
  • Deep understanding of constrained randomization and the development of efficient test suites
  • Experience with code coverage and functional coverage-driven verification methodology.
  • Experience in creating, running and debugging of SystemVerilog/UVM constraint-random testbench.
  • Working knowledge of scripting languages such as Python or Perl
  • Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines

Preferred qualifications:

  • MS CE/EE with 5+ years of industry experience in verification
  • Good verbal and written communication skills
  • Experience of GPU or CPU is a plus
Employers have access to artificial intelligence language tools (“AI”) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
  • Dice Id: xorca001
  • Position Id: 8852733
  • Posted 30+ days ago

Company Info

About Xoriant Corporation

Xoriant is a Sunnyvale, CA headquartered digital engineering firm with offices in the USA, Europe, and Asia. From Tech Startups to Fortune 100 Enterprises, we enable innovation, accelerate time to market, and ensure client competitiveness across industries. Across all our focus areas – platform engineering, cloud, data & and AI, and Security – every solution we develop benefits from our product engineering DNA and culture of innovation. It also includes successful methodologies, framework components, and accelerators for rapidly solving critical client challenges. For 30 years and counting, we have taken great pride in the longlasting, deep relationships we have with our clients.

For further information about Xoriant, please visit our website

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