Senior CIS Pixel Design Engineer

• Full-Time | Open to Consulting (Part-Time ~20 hrs/week)


• Salary: up to $200k base + cash rewards, and the 200k base is more for management level candidate
  


• Open to provide Visa sponsorship or Visa Tranfer for the right candidate

Role Overview

We are seeking an experienced Pixel Design Engineer with direct experience in CMOS Image Sensor (CIS) pixel layout. This is a critical, high-impact role supporting ongoing projects and next-generation pixel development.

This is not a general analog or mixed-signal role-hands-on pixel design experience is required.

You will work closely with a small, highly skilled team to design, optimize, and implement pixel layouts, contributing immediately to active programs.

Key Responsibilities

• Design and optimize CIS pixel layouts (front-end, back-end, and optical structures)


• Perform pixel-level layout optimization considering:
  
  
  
  • Process flow and design rules
  
  
  • Timing constraints and noise performance
  
  
  • Signal interference via capacitance extraction
  
  
  
  


• Develop and implement pixel array floorplans


• Execute DRC, LVS validation across pixel arrays


• Design special pixels (e.g., dark reference pixels)


• Collaborate across teams on pixel-to-readout interfaces


• Contribute to optical structure design and layout alignment

Required Qualifications (Must-Have)

• BS + 5 years OR MS + 3+ years of hands-on CIS pixel layout experience


• Proven expertise with IC layout and parasitic capacitance extraction


• Strong understanding of:


• 
  
  
  
  • CIS pixel physics
  
  
  • Timing and operational principles
  
  
  
  


• Proficiency with EDA tools:
  
  
  
  • Cadence Virtuoso (layout)
  
  
  • Synopsys Sentaurus TCAD (Sprocess, Sdevice, SDE, Raphael)
  
  
  
  


• Programming skills (moderate level)


• Degree in Electrical Engineering, Physics, or Photonics

Important: Analog or mixed-signal-only backgrounds without pixel experience will not be considered.

Preferred Qualifications

• Experience with CMOS image sensor process integration


• Knowledge of device physics and optics


• Prior work on advanced pixel technologies or imaging chips

Work Setup & Flexibility

• Preferred: Onsite in Irvine, CA


• Open to remote candidates (must be able to travel to Irvine ~1 week/month)


• Initial onboarding will require onsite presence


• Travel expenses covered


• Relocation assistance available

Additional Details

• Reports to: Senior Director of Pixel Design


• Team: Small, collaborative R&D group (currently rebuilding pixel team)


• Work Hours: ~9:30/10 AM - 6/7 PM PST (includes collaboration with Asian team)


• Visa Sponsorship: Available

Why Join Us

• Work on cutting-edge camera sensor technology


• High-impact role with immediate contribution expectations


• Small team with strong ownership and innovation culture


• Flexible hiring approach (full-time or consulting options available)