Static Timing Analysis (STA Engineer)

Hi, Job Title: Physical Design Engineer Location: Cupertino, CA Work Mode: 100% Onsite (5 Days/Week) Experience: 5 15Years Job Description We are actively hiring experienced Physical Design Engineers for a leading semiconductor client in Cupertino, CA. Candidates should possess strong expertise in end-to-end physical implementation and signoff flows for advanced node SoC designs. Responsibilities Execute complete physical design implementation flow including Floorplanning, Power Planning, Pla

Job Title: Design Engineer - RTL-to-GDSII Location: Dallas, TX or Sunnyvale, CA Duration: Contract - 11 months Pay Range: $75/hr $81/hr (W2) Job ID: 373412 About BCforward BCforward is a leading global IT consulting and workforce solutions firm providing services and support to Fortune 500 and government clients. Founded in 1998, BCforward has grown with our customers needs into a full-service business solutions provider. With delivery centers and offices across North America and India, we

JobTitle:SeniorDFTEngineer[ATPG,MBIST,IOTest,ClockVerification] Location:SantaClara,CA Experience:4+YearsinDFT JobSummary WeareseekinganexperiencedSeniorDFT/ATPGEngineertosupportNVIDIAshighperformanceGPUandSoCdesigns.TherolefocusesondeliveringrobustDesignforTestability(DFT)solutions,comprehensiveATPG,andadvancedtestfeaturessuchasMBIST,IOTest,andClockVerification,ensuringhighcoverage,yield,andsiliconreliability.TheengineerwillworkcloselywithNVIDIAscrossfunctionalteamstoenablefirsttimerightsilico

Job Title : Senior DFT Engineer Location : Santa Clara, CA Experience : 4+ Years in DFT Skill: [ATPG , MBIST, IO Test, Clock Verification] Job Summary We are seeking an experienced Senior DFT / ATPG Engineer to support highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The enginee