Static Timing Analysis (STA Engineer)

Position: Static Timing Analysis Engineer Location - San Jose, CA, USA What You will Do: Develop and validate timing constraints for intricate SoC designs. Expertise in Synthesis, Equivalency Checking and STA Must have Block Level and Multi-voltage Timing Closure experience. Top Level Timing Closure experience a plus. Experience with Synopsys Tools Synopsys DC/FC for Synthesis, Synopsys Formality for Equivalency Checking and Synopsys PrimeTime for STA Define and implement timing signoff method

Company: Qualcomm Atheros, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm-Atheros, a.k.a. QCA is a wholly owned subsidiary of Qualcomm and a leading provider of wireless technologies for the mobile, networking, computing and consumer electronics markets. As a key member of a fast-paced Integrated Wireless Technology team. The role involves ownership and leading Static timing closure and synthesis for complex low-power WiFi SoCs and sub-syste

Ready to make connectivity from space universally accessible, secure and actionable? Then you've come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services. We are building a highly-advanced low Earth orbit (LEO) space system that will fundamentally change the design, economics, manufacturing and service delivery associated with traditional satellite and terrestrial IoT systems. We're intentional, we're una

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing closure