3nm jobs in Remote

Remote

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Today

Job Title: Physical Design Engineer Location: Remote We are looking for a Physical Design Engineer with hands-on experience in TSMC 3nm/2nm at SOC for cutting-edge GPU / High-Performance designs. Key Responsibilities: 1. Own Netlist-to-GDSII for high-speed, low-power SOC 2. Floorplanning, Placement, CTS, Routing, Timing closure 3. Drive PPA optimization - Power, Performance, Area for 2nm/3nm 4. Handle advanced nodes issues: IR Drop, EM, Crosstalk etc 5. Hands on experience on tools - Synopsys F

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Third Party, Contract

$60+

Physical Design Engineer

Palo Alto, California

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Today

JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivoltage (UPF)Power gating, clock gatingPerform physical verification and signoff:STA (Primetime)SI / CrosstalkIR drop & EM analysisWork on advanced nodes (7

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Contract

Depends on Experience

Physical Design Engineer GPU / High-Performance SoC

Remote

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Today

Job Title: Physical Design Engineer GPU / High-Performance SoC Location: Mountain View, CA (Full Onsite) Openings: 2 Job Description We are looking for an experienced Physical Design Engineer with hands-on experience in advanced semiconductor process nodes, particularly TSMC 3nm and/or 2nm, for high-performance SoC, GPU, or similar complex chip designs. The ideal candidate will have strong end-to-end physical design experience, from netlist to GDSII, along with expertise in PPA optimization, tim

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Contract

$60 - $80

Physical Design Engineer

Palo Alto, California

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14d ago

Position: Physical Design Engineer Location : Palo Alto, CA (Full Onsite) Rate : 90-100/hr Client : HCL/Tesla Job ID : 166019 Number of Positions : 5 JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivolta

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Contract

Depends on Experience

Physical Design Engineer Semiconductor / ASIC

Hybrid in Palo Alto, California

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Today

Physical Design Engineer Semiconductor / ASIC Location: Palo Alto, CA (100% Onsite) Openings: 5 Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification. Key Responsibilities Execute the complete phy

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Contract

$70 - $90

Physical Design Engineer

Austin, Texas

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30+d ago

Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing clo

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Full-time

Depends on Experience

Physical design Engineer

Mountain View, California

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13d ago

Position 1 Physical Design Engineer Mountain View CA (onsite - Hybrid) Mode of hiring: Fulltime permanent Customer wants someone who is having some logical design experience along with PD experience. Having some RTL2PD flow skills such as CDC/RDC/VCLP is preferred. Having some exposure of logic design is also preferred. Canddiate doesn't have to do the logic design, but needs to review the synthesis/PNR report to analyze for the timing/LoL optimization Provides services in transforming the RTL d

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Full-time

$120,000 - $140,000

Sr Data Converter IC Design Engineer (FinFET)

San Diego, California

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Today

Senior / Lead Data Converter IC Design Engineer (FinFET) Location: San Jose CA / San Diego CA Job Type: Full-Time & Contract Options Available Requirements: ship Required Compensation: $150,000 - $180,000 / year + Comprehensive Benefits About the Role We are seeking an experienced Analog/Mixed-Signal IC Design Engineer to architect and tape out high-speed data converters (ADCs/DACs) in advanced FinFET nodes (7nm down to 3nm). You will own the full design cycle-from system architecture to pos

Full-time

USD 150,000.00 - 180,000.00 per year

Sr Data Converter IC Design Engineer (FinFET)

San Jose, California

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Today

Full-time

USD 150,000.00 - 180,000.00 per year

Senior / Lead Data Converter IC Design Engineer (FinFET)

Austin, Texas

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Today

Senior / Lead Data Converter IC Design Engineer (FinFET) Location: San Jose CA / San Diego CA / Remote in USA Job Type: Full-Time & Contract Options Available Requirements: ship / holder Required Compensation: $150,000 - $180,000 / year + Comprehensive Benefits About the Role We are seeking an experienced Analog/Mixed-Signal IC Design Engineer to architect and tape out high-speed data converters (ADCs/DACs) in advanced FinFET nodes (7nm down to 3nm). You will own the full design cycle-from sys

Full-time

USD 150,000.00 - 180,000.00 per year

Senior / Lead Data Converter IC Design Engineer (FinFET)

Rochester, Minnesota

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Today

Full-time

USD 150,000.00 - 180,000.00 per year

Senior / Lead Data Converter IC Design Engineer (FinFET)

Hillsboro, Oregon

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Today

Full-time

USD 150,000.00 - 180,000.00 per year

Sr / Lead Data Converter IC Design Engineer (FinFET)

Chandler, Arizona

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Today

Full-time

USD 150,000.00 - 180,000.00 per year

Senior / Lead Data Converter IC Design Engineer (FinFET)

Burlington, Vermont

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Today

Full-time

USD 150,000.00 - 180,000.00 per year

Senior / Lead Data Converter IC Design Engineer (FinFET)

Raleigh, North Carolina

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Today

Full-time

USD 150,000.00 - 180,000.00 per year

Senior SRAM Layout Design Engineer

Plano, Texas

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16d ago

Role Overview We are seeking a Senior SRAM Layout Design Engineer to own the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies at the leading edge of process scaling. This is a senior individual-contributor role you'll own and contribute blocks alongside an established team of leads, not manage one. The role works closely with circuit design, PnR/integration, CAD, and foundry teams to deliver consistent, hi

Full-time

Depends on Experience

Senior Staff Engineer (Memory/Network Systems Software) - San Jose, CA - Onsite

San Jose, California

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9d ago

Senior Staff Engineer (Memory/Network Systems Software) - San Jose, CA - OnsiteProdapt ASIC Services (formerly Innovative Logic) provides end-to-end SoC/ASIC, FPGA, and embedded software solutions. Their design services cover the complete lifecycle from RTL to GDSII, covering domains like 3nm node physical design, UVM verification, DFT, and silicon bring-up for 5G, AI, and IoT. We are looking for a Senior Staff Engineer (Memory/Network Systems Software) in San Jose, CA for a 5-day onsite positio

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Contract

Depends on Experience

Senior SRAM Layout Design Engineer

Santa Clara, California

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Today

Job description: Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies. Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly. Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows. Support

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Third Party, Contract

$112 - $112

SoC Physical Integration Engineer

San Jose, California

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Today

ADVANCE YOUR CAREER. ADVANCE THE WORLD. At AMD, we believe technology has the power to solve the world's most important challenges. From advancing healthcare and scientific discovery to powering AI and the technologies people rely on every day, innovation at AMD is shaping the future. Whether you're designing next-gen processors, enabling AI breakthroughs, or bringing leading edge products to market, every role at AMD contributes to something bigger - technology that moves the world forward. Joi

Full-time

USD 145,600.00 per year

Synthesis & STA Engineer - High-Speed SerDes

San Jose, California

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Today

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL , Ethernet, NVLink, PCIe , and UALink semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-t

Full-time

USD 160,000.00 - 200,000.00 per year