ASIC jobs in California

ASIC/SOC DFT Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. ASIC/SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 135,000.00 - 175,000.00 per year

ASIC/FPGA Verification Engineer III, Secret Clearance

Poway, California

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8d ago

Job Description Join Our Team as a ASIC/FPGA Verification Engineer where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment. Location: This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in: Denver CO or Highlands Ranch CO Sunnyvale CA You will work a flexible 9x80 schedule in the office full-time. What does this role look like?

Full-time

USD 101,000.00 - 178,135.00 per year

ASIC DFT Staff Engineer

Remote

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2d ago

Job Title: ASIC DFT Staff Engineer Location: Remote Job Description: Key Skills: "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical own

Easy Apply

Third Party, Contract

ASIC/FPGA Design Engineer III, Secret Clearance

Poway, California

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8d ago

Job Description Join Our Team as a ASIC/FPGA Design Engineer where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment. Location: This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in: Sunnyvale CA Denver CO Highlands Ranch CO You will be working a flexible 9x80 schedule in the office full-time. About Lockheed Martin Space Spac

Full-time

USD 101,000.00 - 178,135.00 per year

ASIC Design Hardware Engineer - SDC/STA - San Jose, CA (Hybrid)

Hybrid in San Jose, California

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3d ago

ASIC Design Hardware Engineer - SDC/STA (Hybrid) Location: San Jose, California, United States of America You are a diligent Design / SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will develop timing constrains at both block level and fu

Easy Apply

Third Party, Contract

$70+

ASIC/FPGA Verification Engineer IV

Poway, California

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8d ago

Job Description Join Our Team as a ASIC/FPGA Verification Engineer where you will work on the development of a sophisticated state-of-the-art avionics product in a world class Integrated Product Development environment. Location: This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facility in: Sunnyvale CA Denver or Highlands Ranch CO You will be working a flexible 9x80 schedule in the office full-time. About Lockheed Martin Space

Full-time

USD 123,500.00 - 217,695.00 per year

Sr. ASIC DFT Engineer (Silicon)

Irvine, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 165,000.00 - 260,000.00 per year

Sr. ASIC DFT Engineer (Silicon)

Palo Alto, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's

Full-time

USD 175,000.00 - 280,000.00 per year

Senior ASIC CAD Engineer

California

•

Today

Our Mission At Palo Alto Networks , we're united by a shared mission-to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you're ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you're in the right place. Who We Are In order to be the cybersecurity partner of choice, w

Full-time

USD 173,600.00 - 280,700.00 per year

ASIC/FPGA Verification Engineer III

Poway, California

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8d ago

Full-time

USD 101,000.00 - 178,135.00 per year

ASIC/RTL Design Engineer

San Jose, California

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10d ago

Job Description: The work will expose the designer to a number of IP including ARM cores, Ethernet, DDR, DMA, PCIE, SATA and internal IPs. Successful candidates will be responsible for leading, and participating in, the design of leading edge SoC?s in advanced digital CMOS processes.Our RTL Design Engineers are expected contribute in all aspects of SoC design including: Chip definition, Architecture development and modeling, Development of micro-architectural specifications, Conversion of micro

Easy Apply

Third Party, Contract

Depends on Experience

Digital Engineer (FPGA/ ASIC)

Los Angeles, California

•

Today

Location: Los Angeles, CA Salary: $70.00 USD Hourly - $95.00 USD Hourly Description: Job Title: Digital Engineer (FPGA/ ASIC) Duration: 1+ year (Possible extension or Perm) Location: About the Role We are looking for you to join our team as a Principal Digital Engineer based out of Woodland Hills, CA. As a Principal Digital Engineer you will have a challenging and rewarding opportunity to be a part of our Enterprise-wide digital transformation. Using Model-based Engineering, DevSecOps and Agil

Contract

Compensation information provided in the description

Physical Design Engineer

San Jose, California

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25d ago

Position: Physical Design Engineer Location: San Jose, CA Hybrid Duration: 12 Months VISA: H-1, USC Position Overview We are seeking an experienced Physical Design Engineer to support the implementation of high-performance semiconductor designs targeting advanced process technologies. This contract position will focus on synthesis, floorplanning, physical implementation, and performance optimization for complex, timing-sensitive designs while working closely with cross-functional engineering

Easy Apply

Third Party

$$70-$80 C2C

Remote (PST time zone preferred) -- Lead ASIC DFT Engineer

San Jose, California

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19d ago

Hello Professional, Good Afternoon Please find the job description give below, if interested please share me your most updated copy of resume. Role: Lead ASIC DFT Engineer Work Setup: Remote, PST time zone preferred Experience Required:10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep tec

Easy Apply

Contract, Third Party

Depends on Experience

Technical Leader Network SDK QA | Saratoga, CA

Saratoga, California

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6d ago

We are seeking a hands-on Technical Leader Network SDK QA to lead the quality strategy for next-generation switching platforms. In this role, you will own SDK validation, design automated test frameworks, mentor QA engineers, and collaborate with SDK, ASIC, and Network OS teams to ensure reliable, high-performance software releases. Required Skills: 8+ years of QA/validation experience in networking SDKs, Network OS, or embedded systemsStrong knowledge of L2/L3 networking, ACLs, QoS, and multica

Easy Apply

Full-time

Depends on Experience

ASIC Manufacturing Project Architect

San Jose, California

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2d ago

Were hiring for a full-time opportunity with a leading semiconductor R&D organization in USA. This role focuses on ASIC Manufacturing Project Architect. Detailed job description is given below. Please share your resume to Job Title: Project Architect Backend (ASIC Manufacturing / Semiconductor) Location:San Jose, CA (Onsite) Type: Full-Time | Direct Hire with End Client Experience:10+ Years Job Summary We are seeking an experienced Project Architect to lead technical customer engagement

Easy Apply

Full-time, Third Party

Depends on Experience

Senior ASIC RTL DESIGN Engineer

Remote or Hybrid in Boston, Massachusetts

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10d ago

12 Months + CONTRACT Starting in September SKILLS: SENIOR ASIC RTL Design Verilog High Speed Memory Interface Experience Logic synthesis & Timing constraints Forward Error Correction (FEC), Bit Rate Error (BER) calculations Integrating Soft IP from Industry Standard and Custom IP into the design Bandwidth calculation Prefer experience with some of: LPDDR5 UFS/FlashPCIe Gen4/5

Easy Apply

Contract

90 - 130

ASIC Emulation Engineer

San Jose, California

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19d ago

Key Skills:Veloce, Palladium, or ZeBu, PCIe and UCIe and memory technologies such as LPDDR and HBM Set up and maintain Siemens Veloce emulation and prototyping platforms Adapt SoC designs for Emulation and Prototyping Develop and debug emulation testbenches and system-level environments Support pre-silicon validation, power/performance analysis, and early software bring-up. Participate in silicon bring-up and validation. Collaborate with design and verification teams to isolate design issues and

Easy Apply

Contract

60 - 75

Lead ASIC DFT Engineer

Remote

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20d ago

Role: Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 10+ yrs to 15 yrs. Job Description: We are seeking a highly experienced Lead ASIC DFT Engineerto architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts a

Easy Apply

Third Party, Contract

110 - 120

High-Speed EDA/CAD Engineer (Analog & Mixed Signal)

Sunnyvale, California

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6d ago

Position:High-Speed EDA/CAD Engineer (Analog & Mixed Signal) Location:Sunnyvale, CA Hybrid 3 days onsite (relocation candidates is fine) Duration:24+ month contract Domain:Analog & Mixed Signal EDA/CAD Job Description: Client is seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the high-speed analog ASIC design team. The engineer will be hands-on with all phases of tool flow, including PDK installation and support, tool support and installation, layou

Easy Apply

Contract

$60 - $70

ASIC jobs in California, USA