Senior DFT Engineer [ATPG, MBIST, IO Test, Clock Verification]
Client- Confidential
Location: Santa Clara, CA
Onsite
Experience: 4+ Years in DFT
Job Summary
We are seeking an experienced Senior DFT / ATPG Engineer to support NVIDIA s highperformance GPU and SoC designs. The role focuses on delivering robust Design for Testability (DFT) solutions, comprehensive ATPG, and advanced test features such as MBIST, IO Test, and Clock Verification, ensuring high coverage, yield, and silicon reliability. The engineer will work closely with NVIDIA s crossfunctional teams to enable firsttimeright silicon and highquality products.
Key Responsibilities
Architect, implement, and validate DFT solutions to improve controllability and observability in complex GPU/SoC designs
Lead scan-based DFT implementation, including scan insertion, compression, and test logic integration
Develop and debug ATPG patterns targeting stuckat, transition, and additional fault models
Implement and support MBIST architectures for onchip memory test, diagnosis, and coverage improvement
Perform IO Test planning and validation to ensure reliable interface and pinlevel testing
Support clock DFT and clock verification, including clock controllability, observability, and atspeed test enablement
Analyze fault coverage reports and drive improvements while balancing power, performance, and area constraints
Collaborate closely with RTL, physical design, verification, and product engineering teams
Support pattern simulation, silicon bringup, manufacturing test debug, and yield ramp
Perform root cause analysis for test escapes and manufacturing failures
Document DFT methodologies, test strategies, and best practices aligned with NVIDIA quality standards
Required Skills & Qualifications
4+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs
Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing
Proven expertise in ATPG pattern generation, analysis, and debug
Experience with MBIST, including memory test architectures and diagnostics
Knowledge of IO Test methodologies for interface and pinlevel validation
Solid understanding of clock DFT and clock verification concepts
Strong grasp of digital design and RTL fundamentals
Experience with industrystandard DFT/ATPG EDA tools
Ability to work effectively in fastpaced, highperformance semiconductor programs
Strong analytical, problemsolving, and communication skills
Preferred Qualifications
B-Tech , BE or equivalent degree in Electronics domain.
Experience with silicon bring-up and production test support
Exposure to advanced nodes and complex SoC & GPU architectures
Exposure to lowpower and performanceaware DFT techniques
Experience supporting highvolume production and yield optimization
Knowledge of low-power and performance-aware DFT techniques
Experience working in high-volume manufacturing environments
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