ASIC jobs in California

Santa Clara, California

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Today

Our Mission At Palo Alto Networks , we're united by a shared mission-to protect our digital way of life. We thrive at the intersection of innovation and impact, solving real-world problems with cutting-edge technology and bold thinking. Here, everyone has a voice, and every idea counts. If you're ready to do the most meaningful work of your career alongside people who are just as passionate as you are, you're in the right place. Who We Are In order to be the cybersecurity partner of choice, w

Full-time

USD 173,600.00 - 280,700.00 per year

Sr. SOC/ASIC DFT Engineer (Silicon Engineering)

Sunnyvale, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the worl

Full-time

USD 170,000.00 - 230,000.00 per year

Sr. ASIC/SOC Verification Engineer (Silicon Engineering)

Sunnyvale, California

•

Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the

Full-time

USD 170,000.00 - 230,000.00 per year

Senior ASIC/RTL Design Engineer

San Jose, California

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Today

We are looking for a Senior ASIC/RTL Design Engineer for our client in San Jose, CA Job Title: Senior ASIC/RTL Design Engineer Job Location: San Jose, CA Job Type: Contract Job Description: Pay Range: $62.45hr - $78.78hrRequirement/Must Have: 5+ years of ASIC design experience.Proven track record of ASIC design across multiple production tape-outs.Experience designing RTL blocks for SoC architectures.Experience integrating ASIC IP into SoCs.Experience with linting, CDC, and RDC methodologies.Ex

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Third Party, Contract

Depends on Experience

Design Verification Engineer

Remote or Toronto, Ontario

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Today

RequirementsKnowledge of semiconductor ASIC design/verification methodologies and flows Working knowledge of Verilog/SystemVerilog/UVM Strong programming skills including object-oriented programming Working experience with digital logic design and verification Practical experience in D2D, NOC, AXI, Ethernet, DDR/LPDDR, HBM, Security, Networking, ARM CPU subsystems Demonstrates good analysis, problem-solving, and critical thinking skills Effective interpersonal, teamwork, and communication skills

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Contract

Depends on Experience

ASIC Physical Design Engineer

San Jose, California

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Today

Job Description We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and delivers advanced System-on-Chip solutions across multiple emerging technologies. They provide high-performance custom solutions for cutting-edge applications. You'll collaborate with customers, frontend, and integration teams to ensure successful tape-outs, contributing across all phases of physical design. Profile of preferred candidate includes 10 + years of han

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Full-time

$180,000 - $220,000

FPGA Design/Verification Engineer

Sunnyvale, California

•

Today

Location: Sunnyvale, CA Salary: $90.00 USD Hourly - $100.00 USD Hourly Description: Job Title: FPGA Design/Verification Engineer Duration: 6+ Months (Possible Extension) Location: Sunnyvale, CA, Possible: onsite Denver CO. Job Description: The selected candidate will be responsible for ASIC & FPGA verification on R&D program. This engineer will be a verification UVM expert. This engineer with have experience: -Verifying FPGA and/or ASIC designs including creating UVM verification environ

Contract

Compensation information provided in the description

System Level Test Engineer

Santa Clara, California

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Yesterday

Job Description & Skill Requirement: System Level Test Engineer that works on system level diag, verification and post-silicon validation of some of the industry''s most complex semiconductor chips. What you''ll be doing: Develop and improve all aspects of testing Nvidia''s SOC products. Your duties include characterization, QA, test, yield enhancement and spec validation. Partner with other engineering groups including ASIC, ATE, DFT, silicon validation, fab process, software and quality te

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Full-time

80,000 - 90,000

FPGA Verification Engineer

Hybrid in San Jose, California

•

Yesterday

Job Title: FPGA Verification Engineer Location: Hybrid (4 days at Cisco SJ office and 1 day remote) Duration: 12 months Rounds of interview: There will be a total of 2 rounds: 1 screening, the second will be in-depth with 2 engineers" Job Description Own verification of entire FPGA design used in high-end router products. Understand design specifications and interact with design engineers to identify verification scenarios. Create test plans, constrained-random verification environments, t

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Contract

Depends on Experience

DFT Engineer

Hybrid in Santa Clara, California

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19d ago

Job Title: DFT Engineer (6+ Years) Location: Santa Clara, California, USA Employment Type: Full-Time Job Summary We are seeking a highly skilled and motivated DFT Engineer with 6+ years of experience to join our team in Santa Clara, CA. The ideal candidate will have strong expertise in Design for Testability (DFT) methodologies, test insertion, and validation for complex SoCs. You will work closely with design, verification, and product engineering teams to ensure high-quality, testable silicon

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Full-time

Depends on Experience

FPGA Verification Engineer

San Jose, California

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6d ago

Position: FPGA Verification Engineer Location: San Jose, CA - Onsite Job Description & Responsibilities Own verification of entire FPGA design used in high-end router productsUnderstand design specifications and interact with design engineers to identify verification scenariosCreate test plans, constrained-random verification environments, test cases, regressions, and coverage reportsIdentify and write all types of coverage measures for stimulus and corner-casesQualifications Strong academic ba

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Contract

Depends on Experience

FPGA Verification Engineer

San Jose, California

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6d ago

ResponsibilitiesOwn verification of entire FPGA design used in high-end router productsUnderstand design specifications and interact with design engineers to identify verification scenariosCreate test plans, constrained-random verification environments, test cases, regressions, and coverage reportsIdentify and write all types of coverage measures for stimulus and corner-casesQualificationsStrong academic background in Electrical Engineering (Bachelors required, Masters preferred)710 years of pur

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Full-time

Depends on Experience

ASIC Implementation Engineer

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power planning and analysis, timing closure, signal int

Full-time

USD 141,300.00 - 226,000.00 per year

Senior ASIC DV Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: You will contribute to the development of complex SOCs targeted towards Touch Controllers/Wireless Charging Chips and other new initiatives. As a verification engineer, your responsibilities will include: Architecting block and full-chip verification e

Full-time

USD 141,300.00 - 226,000.00 per year

ASIC/FPGA Verification/Emulation Engineer IV

Poway, California

•

Today

Job Description Join Our Team as an ASIC/FPGA Verification/Emulation Engineer where you will support over 50 different programs and research and development (R&D) efforts, affecting technology across military space, civil space, commercial space, missiles, missile defense platforms, satellite surveillance platforms, deep space exploration, and manned flight missions. Location: This position does not support teleworking; the selected candidate will be located near our Lockheed Martin Space facil

Full-time

USD 123,500.00 - 217,695.00 per year

Senior DSP and ASIC Engineer

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: We are looking for a design engineer to work on challenging high speed design of complex modules for Ethernet and PCIE Serdes cores used across multiple chips. You will be responsible for the modeling and simulations of DSP algorithm and implementation

Full-time

USD 120,000.00 - 192,000.00 per year

ASIC Methodology Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: The DTECH team is part of the Global SOC organization and is responsible for STA methodology and signoff, foundry technology enablement and analysis, design automation and internal and external EDA tools, design analysis and optimization tools and platforms, low power architecture, methodology, and IP, and foundation IP development. About the Role As a member of the DTECH

Full-time

USD 153,200.00 - 229,800.00 per year

ASIC Development Engineer

San Jose, California

•

Today

Company Description Job Description Designer will be responsible for the design of high performance analog and mixed-signal circuit blocks. Responsibilities include transistor level, block level and module level circuit architecture, design, simulation, optimization, layout supervision, layout verification, preparation of test plan for the test group, product characterization, reliability and yield assessment and modeling, simulation to bench and bench to test correlation, bench evaluation bot

Full-time

USD 170,600.00 per year

ASIC Timing and Methodology Engineer

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a Timing Engineer, you will play a vital role in Timing analysis targeting the Mobile, Compute, Automotive and IOT markets The candidate will work with best-in-class methodologies, tools and technology to design innovative SOC products at the block/IP-level and at system-level in 5nm, 4nm and beyond (process technologies).You will be working with physical design team (an

Full-time

USD 140,000.00 - 210,000.00 per year

ASIC DFT Engineer

San Jose, California

•

Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is seeking candidates for a Staff DFT engineer position. The successful candidate will be responsible for developing and implementing DFx (Design for Test/debug & manufacturability) solutions for Digital, mixed signal IPs. Candidate will also

Full-time

USD 120,000.00 - 192,000.00 per year

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ASIC jobs in California, USA