ASIC Jobs in California

1 - 20 of 3,118 Jobs

Low Power Principal Engineer/ASIC EngineerJob Title - Low Power Principal Engineer/ASIC Engineer

SivaltechCompany Name - Sivaltech

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San Diego, California, USA

Full-time, Third Party

"Exciting Opportunity! We're seeking a Low Power Principal Engineer/ASIC Engineer to join our team in San Diego, CA! Key Responsibilities: - Low power design and verification (UPF, VCLP) - Power analysis and optimization (PTPX) - STA and timing analysis - Synthesis and physical design (DC synthesis) Requirements: - 5+ years of experience in ASIC design, low power design, and verification - Proficiency in scripting languages (Shell, TCL, Perl, Python) - Experience with VCLP, PTPX, Formality,

Senior ASIC Design EngineerJob Title - Senior ASIC Design Engineer

PeopleNTechCompany Name - PeopleNTech

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San Jose, California, USA

Third Party, Contract

What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components.Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology.Option to engage in block-level RTL design or block or top-level IP integration.Collaborate with Software, Design, and Verification teams to validate the functional and performance objectives of the S

Senior ASIC Design EngineerJob Title - Senior ASIC Design Engineer

PeopleNTechCompany Name - PeopleNTech

•

San Jose, California, USA

Third Party, Contract

Position: Senior ASIC Design Engineer Location: San Jose, CA (Complete onsite) Experience: 8+ years (Relevant) What candidate will Be Doing: Map multi-million gate SoC designs onto prototyping platforms, creating design partitions, FPGA builds, and testbenches to simulate FPGA components. Establish prototyping systems in the lab and contribute to defining, evolving, and supporting our prototyping methodology. Option to engage in block-level RTL design or block or top-level IP integration. Colla

SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)Job Title - SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)

SpaceXCompany Name - SpaceX

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Irvine, California, USA

Full-time

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband in

Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)Job Title - Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)

SpaceXCompany Name - SpaceX

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Irvine, California, USA

Full-time

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadban

ASIC Package SI/PI EngineerJob Title - ASIC Package SI/PI Engineer

Datum Software, Inc.Company Name - Datum Software, Inc.

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San Jose, California, USA

Contract, Third Party

Job Description: ASIC Package SI/PI Engineer Location: San Jose, CA 100% Onsite ASIC Package Engineer SI/PI Responsibilities: Drive chip-package-system co-design by driving signal and power integrity requirements analysis and optimizationDefine power tree structure, netlists, etc for High Performance Computing based on 2.5D/3D package technologyRun pre-layout and post-layout simulation flow with a focus on high-speed interface and PDN, create simulation models and develop simulation methodology

Sr. DSP R&D Engineer - C/C++, Wireline, Simulink, ASICJob Title - Sr. DSP R&D Engineer - C/C++, Wireline, Simulink, ASIC

Motion Recruitment Partners, LLCCompany Name - Motion Recruitment Partners, LLC

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Irvine, California, USA

Full-time

Our client is a glbal infrastructure technology leader built on more than 60 years of innovation within the semiconndutor and Manufacturing space for communications. They are urgently seeking a Sr. level Digital Signal Processing (DSP) R&D Engineer to join their growing team. Responsibilities include: Develop specification, architecture, and micro-architecture of digital signal processing and communications algorithms Bit-exact MATLAB/Simulink and C/C++ system modeling and simulation Develop and

ASIC EngineerJob Title - ASIC Engineer

AdientOne LLCCompany Name - AdientOne LLC

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California, USA

Contract

Role: ASIC Engineer Location: Clara CA 95054 OR Longmont CO 80503 Duration: 12+months Job Description: Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scrip

ASIC Engineer, ImplementationJob Title - ASIC Engineer, Implementation

Meta Platforms, Inc. (f/k/a Facebook, Inc.)Company Name - Meta Platforms, Inc. (f/k/a Facebook, Inc.)

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Sunnyvale, California, USA

Full-time

Meta Platforms, Inc. (f/k/a Facebook, Inc.) has the following positions in Sunnyvale, CA ASIC Engineer, Implementation: Run logic/physical synthesis using advanced optimization techniques and generate optimized gate level netlist for Timing, Area, and Power. (ref. code REQ-2503-148357: $141,682/year - $154,000/year). Individual pay is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base salary only, and do not include bonus

PCB Design EngineerJob Title - PCB Design Engineer

Yom Solutions LLCCompany Name - Yom Solutions LLC

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Santa Clara, California, USA

Full-time

Role: PCB Design EngineerLocation: Santa Clara, CA ( Day 1 Onsite)Type: Fulltime/Contract to hire and subcon Job Description: Senior Electrical Engineer - Advanced Semiconductor Packaging and Integration Company OverviewJoin our team and be at the forefront of semiconductor technology innovation. We are looking for a highly skilled Senior Engineer to contribute to our cutting-edge projects in Advanced Semiconductor Packaging and AI. You will work alongside some of the brightest minds in the indu

ASIC Engineer, Formal VerificationJob Title - ASIC Engineer, Formal Verification

VeearCompany Name - Veear

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Sunnyvale, California, USA

Contract

Requirements: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.5+ years of experience in Formal VerificationExperience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etcProven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniquesProven analytical skills to craft Client solutions to tackle industry-le

ASIC Design EngineerJob Title - ASIC Design Engineer

Yochana IT SolutionsCompany Name - Yochana IT Solutions

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Santa Clara, California, USA

Contract, Third Party

ASIC Design Engineer Location: Santa Clara, CA Onsite Contract Overview of the Role As an ASIC Design Engineer , you will play a crucial role in the development and optimization of our cutting-edge ASIC solutions. Your work will directly impact the efficiency, performance, and scalability of our products, driving forward the company's objectives and contributing to technological innovations that shape the industry. Detailed Responsibilities Run and manage Fusion Compiler, ICC II, and Innovus

Principal Verification EngineerJob Title - Principal Verification Engineer

OSI Engineering, Inc.Company Name - OSI Engineering, Inc.

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San Jose, California, USA

Full-time

A leading chip and silicon IP provider is looking to hire a talented Principal Verification Engineer to join its Memory Interconnect Design team in either San Jose, CA or Morrisville, NC. This is a great opportunity to work alongside some of the industry's top engineers to help develop cutting-edge technologies that accelerate and secure data. In this full-time role, the Principal Verification Engineer will report to the Director of Design Engineering and take a key role in product development a

ASIC & FPGA EngineerJob Title - ASIC & FPGA Engineer

Sun Technologies,Inc.Company Name - Sun Technologies,Inc.

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Remote

Contract

Job Title: ASIC & FPGA Engineer Duration: up to 12 months contract (with the possibility of extension) Location: Remote Work / Work from Home Pay Range: $85 - $90/hr on W2 Featured Benefits: Medical Insurance in compliance with the ACA401(k)Sick leave in compliance with applicable state, federal, and local laws Job Description: Responsible for ASIC & FPGA developmentExperience in developing, testing, and integrating FPGA platformsCollaboration with Software Engineers and other ASIC/FPGA engine

ASIC Engineer (Design Verification)Job Title - ASIC Engineer (Design Verification)

CloudiousCompany Name - Cloudious

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Sunnyvale, California, USA

Third Party, Contract

ASIC Engineer (Design Verification) Bay Area, CA or Austin, TX 12 Months Responsibilities Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification. Develop functional tests based on verification test plan. Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage. Debug, root-cause and resolve functional failures in the design, partnering with the Design team. Collab

Analog Mixed Signal ASIC EngineerJob Title - Analog Mixed Signal ASIC Engineer

DraperCompany Name - Draper

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Remote or Cambridge, Massachusetts, USA

Full-time

Overview: Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas

Principal Analog Mixed Signal ASIC EngineerJob Title - Principal Analog Mixed Signal ASIC Engineer

DraperCompany Name - Draper

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Remote or Cambridge, Massachusetts, USA

Full-time

Analog Mixed-Signal ASIC EngineerJob Title - Analog Mixed-Signal ASIC Engineer

DraperCompany Name - Draper

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Remote or Clearfield, Utah, USA

Full-time

ASIC Implementation EngineerJob Title - ASIC Implementation Engineer

Broadcom CorporationCompany Name - Broadcom Corporation

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San Jose, California, USA

Full-time

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom develops critical Infrastructure chips that enable a variety of Customers to produce ASICs in almost all major segments of the Semiconductor industry, including AI. Be part of the Design Implementation team within Broadcom ASIC Products Divis

ASIC Verification EngineerJob Title - ASIC Verification Engineer

Broadcom CorporationCompany Name - Broadcom Corporation

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San Jose, California, USA

Full-time

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Job duties: Functional verification of complex designs, especially external interfacing IPs/memory controllers.Responsible for all aspects of verification from test planning, test bench development, test execution and functional/code coverage closure.