LVS jobs in California

Physical Design Engineer Semiconductor / ASIC

Hybrid in Palo Alto, California

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Today

Physical Design Engineer Semiconductor / ASIC Location: Palo Alto, CA (100% Onsite) Openings: 5 Job Overview We are looking for an experienced Physical Design Engineer with strong hands-on expertise in end-to-end ASIC physical design and advanced semiconductor process nodes. The ideal candidate must have exposure to TSMC 2NP/3NP technology and proven experience in physical implementation, timing closure, power optimization, and physical verification. Key Responsibilities Execute the complete phy

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Contract

$70 - $90

Analog Layout Engineer

San Jose, California

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Today

Job Title: Analog Layout Engineer (592074) Location: San Jose, CA (Onsite) Description As an Analog Layout Engineer, you will be responsible for: Layout of Analog / High Speed transceiver circuit blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc. in a timely manner. Layout of sensitive active / passive components including resistors, capacitors and inductors. Design verification including DRC, LVS, ERC and ANT and extraction. Block level floor planning with design engineers. R

Full-time

Physical Design Engineer

Palo Alto, California

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14d ago

Position: Physical Design Engineer Location : Palo Alto, CA (Full Onsite) Rate : 90-100/hr Client : HCL/Tesla Job ID : 166019 Number of Positions : 5 JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivolta

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Contract

Depends on Experience

Staff Engineer, SRAM Circuit Design

San Jose, California

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Today

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries o

Full-time

USD 163,000.00 - 253,000.00 per year

Layout Automation Engineer

Calabasas, California

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Today

Overview Keysight is at the forefront of technology innovation, delivering breakthroughs and trusted insights in electronic design, simulation, prototyping, test, manufacturing, and optimization. Our ~15,000 employees create world-class solutions in communications, 5G, automotive, energy, quantum, aerospace, defense, and semiconductor markets for customers in over 100 countries. Learn more about what we do. Our award-winning culture embraces a bold vision of where technology can take us and a

Full-time

USD 143,050.00 - 238,420.00 per year

Sr. Engineer, Layout Design

Santa Clara, California

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3d ago

About SiTime SiTime is the Precision Timing company. Timing is the heartbeat of all electronics, ensuring performance, resilience and scalability. For decades, quartz devices, non-silicon technology, have kept systems in sync, but they struggle in harsher, more demanding environments. MEMS-based Precision Timing delivers greater accuracy, smaller size and resilience. Today, MEMS timing powers over 400 applications, including high-growth ones in AI datacenters, automated driving, industrial and

Full-time

USD 124,920.00 - 171,770.00 per year

Staff RF Hardware Engineer - Device Technology

San Diego, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: As a member of the Qualcomm Si Process Packaging Solutions (PPS) team, this candidate will drive Si process technology evaluation, development, design enablement and productization for Mixed-Signal/RF products at foundry partners. Responsibilities Drive bulk Si and RFSOI technology evaluation, development and design enablement for RFFE designs, including RF switching and a

Full-time

USD 145,600.00 - 218,400.00 per year

Senior Physical Verification CAD Engineer

Mountain View, California

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Today

Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft's expanding Cloud Infrastructure and responsible for powering Microsoft's "Intelligent Cloud" mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and complian

Full-time

USD 119,800.00 - 234,700.00 per year

Senior Software Engineer

Calabasas, California

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Today

Full-time

USD 129,450.00 - 215,740.00 per year

Senior Backend Design Automation Engineer - New Process Node Enablement

San Jose, California

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Today

Job Details: Job Description: About Altera At Altera , our independence as the world's largest pure-play FPGA solutions provider gives us the focus, speed, and agility to innovate without compromise. With more than four decades of industry-leading FPGA expertise, our singular mission is to deliver the programmable technologies that help customers differentiate, innovate, and scale across rapidly evolving markets like AI, cloud, networking, and edge. As an independent company, we move faster,

Full-time

USD 149,100.00 - 215,925.00 per year

MTS SoC DFT Engineer, HBM

Folsom, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern d

Full-time

USD 199,000.00 - 347,000.00 per year

Senior Application Engineer

Calabasas, California

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Today

Full-time

USD 156,740.00 - 261,230.00 per year

Senior Principal Analog Methodology Engineer

Santa Clara, California

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Today

Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute. As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team - we'd

Full-time

USD 225,500.00 - 338,500.00 per year

Senior Engineer, Physical Design AI/ML

San Jose, California

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Today

Full-time

USD 138,000.00 - 206,000.00 per year

RFIC Layout Engineer

Irvine, California

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Today

Do you have a passion for invention and self-challenge? Do you thrive with pushing the limits of what's considered feasible? As part of an outstanding `team, you'll craft sophisticated, groundbreaking projects that deliver more performance in our products than ever before. You'll work across fields to transform improved hardware elements into a single, coordinated design. Join us, and you'll help us innovate new technologies that continually outperform the previous iterations! By collaborating w

Full-time

Staff Digital Physical Implementation and Integration Engineer

San Jose, California

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Today

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. As a Design Engineer at Micron Technology, Inc., you will be responsible for designing and analyzing digital and analog circuits used in the development of memory products! We are engaged in develo

Full-time

USD 145,000.00 - 246,000.00 per year

Senior SRAM Layout Design Engineer

Santa Clara, California

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Today

Job description: Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies. Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly. Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows. Support

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Contract, Third Party

$112 - $112

Electronic Design Engineering, Senior

Newport Beach, California

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Today

MACOM (NASDAQ: MTSI) is a global leader in the design and manufacture of advanced semiconductor products across a diverse range of end markets, including Data Centers, Telecommunications, Industrial and Aerospace and Defense. We develop innovative, cutting-edge technologies and products across the spectrum of radio frequency (RF), microwave, millimeter wave, photonics and high-speed analog technologies. Our solutions support critical network infrastructure applications like artificial intelligen

Full-time

USD 107,000.00 - 139,000.00 per year

ASIC Implementation Engineer PD

San Jose, California

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Today

Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account) 2. If you already have a Candidate Account, please Sign-In before you apply. Job Description: Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next generation Artificial Intelligence and PCIe Switch Pro

Full-time

USD 121,900.00 - 195,000.00 per year

Physical Design Engineer

Palo Alto, California

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Today

JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivoltage (UPF)Power gating, clock gatingPerform physical verification and signoff:STA (Primetime)SI / CrosstalkIR drop & EM analysisWork on advanced nodes (7

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Contract

Depends on Experience

LVS jobs in California, USA