LVS jobs in South San Francisco, CA

Mountain View, California

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5d ago

Description: Seeking an experienced Analog Layout Engineer with TSMC N3 experience. Youll create high-quality, manufacturable analog layouts, collaborate with design engineers, and ensure designs meet electrical and DRC/LVS requirements. Requirements: Proven analog IC layout experience (TSMC N3 or similar) Proficiency with layout tools (Cadence Virtuoso, Synopsys, or equivalent) Strong understanding of analog performance, matching, and parasitics

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Contract

Depends on Experience

AI Silicon Physical Design Engineer

Sunnyvale, California

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Today

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras works with the leading model labs, global enterprise

Full-time

USD 150,000.00 - 250,000.00 per year

Sr Director, Applications Engineering

Sunnyvale, California

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Today

Descriptions & Requirements Job Description and Requirements We Are Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You

Full-time

Analog IC Layout Engineer

South San Francisco, California

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Today

About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional

Full-time

USD 83,000.00 - 139,000.00 per year

Analog Layout Engineer

Oakland, California

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Today

Analog Layout Engineer Bay Area,CA (onsite) Longterm Contract Position OverviewWe are looking for an experienced Analog Layout Engineer with 8+ years of industry experience in advanced semiconductor process technologies. The ideal candidate will have strong expertise in high-speed analog/mixed-signal layout and hands-on experience with advanced 2nm, 3nm, and 5nm process nodes.The role involves ownership of complex analog and mixed-signal layout blocks, working closely with circuit designers and

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Contract, Third Party

Depends on Experience

EDA/CAD Engineer (Analog & Mixed Signal)

Hybrid in Sunnyvale, California

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6d ago

EDA/CAD Engineer (Analog & Mixed Signal) Sunnyvale, CA Hybrid 3 days onsite (relocation candidates is fine) 12 Months 2 video calls Job Description: Seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the high speed analog ASIC design team. The engineer will be hands-on with all phases of tool flow including PDK installation and support, tool support and installation, layout support, design support including schematic and simulation, design archive and tapeout

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Contract

75 - 80

High-Speed EDA/CAD Engineer (Analog & Mixed Signal)

Sunnyvale, California

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6d ago

Position:High-Speed EDA/CAD Engineer (Analog & Mixed Signal) Location:Sunnyvale, CA Hybrid 3 days onsite (relocation candidates is fine) Duration:24+ month contract Domain:Analog & Mixed Signal EDA/CAD Job Description: Client is seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the high-speed analog ASIC design team. The engineer will be hands-on with all phases of tool flow, including PDK installation and support, tool support and installation, layou

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Contract

$60 - $70

Physical Design Engineer & DV Engineers

Sunnyvale, California

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20d ago

Job Title:PhysicalDesignEngineer(PD/PnR) Location Bay Area CA / Austin TX (Hybrid) Job Summary Seeking aPhysicalDesignEngineerwith strong hands-on experience in block-level and top-level Place & Route using Synopsys Fusion Compiler. The candidate will be responsible for implementation, timing closure, low-power integration, and signoff activities for complex SoCdesigns. Key Responsibilities Perform block-level and top-levelPhysicalDesignimplementation using Fusion Compiler. Drive floorplannin

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Full-time

160,000 - 170,000

Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

Palo Alto, California

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Today

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. FULL CHIP PHYSICAL VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system.

Full-time

USD 175,000.00 - 280,000.00 per year

Senior Staff GPU Physical Design Engineer

Remote

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Today

Job Description Title: Senior Staff GPU Physical Design Engineer Location: Austin, TX or San Jose, CA. onsite strongly preferred Need: GPU or high-performance SoC experience. Advanced node (?5nm). Full block ownership Position Summary We are seeking a Senior Staff GPU Physical Design Engineer for our client to work on the physical implementation of high-performance GPU and system-level IP, driving execution across synthesis, place-and-route, timing closure, and signoff for their advanced tech

Contract

Application Engineering, Sr Staff Engineer - Runset Development

Sunnyvale, California

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Today

Descriptions & Requirements Job Description and Requirements We Are Synopsys is the leader in engineering solutions from silicon to systems, helping customers accelerate innovation in the era of pervasive intelligence. From AI and cloud infrastructure to automotive and mobile technologies, our solutions power the advanced chips and systems shaping the future. We combine industry-leading silicon design, IP, simulation, and analysis solutions with deep customer partnership to help innovators move

Full-time

Applications Engineering, Staff Engineer

Sunnyvale, California

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Today

Descriptions & Requirements Job Description and Requirements We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a season

Full-time

Senior Integration/API architect

Palo Alto, California

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Today

PsiQuantum's mission is to build the first useful quantum computers-machines capable of delivering the breakthroughs the field has long promised. Since our founding in 2016, our singular focus has been to build and deploy million-qubit, fault-tolerant quantum systems. Quantum computers harness the laws of quantum mechanics to solve problems that even the most advanced supercomputers or AI systems will never reach. Their impact will span energy, pharmaceuticals, finance, agriculture, transportati

Full-time

USD 165,000.00 - 185,000.00 per year

Senior Physical Verification CAD Engineer

Mountain View, California

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Today

Overview Do you have a passion for advanced silicon signoff and physical verification at leading-edge technology nodes? You will be part of a team responsible for driving state-of-the-art Physical Verification CAD solutions for Microsoft's silicon design teams. In this role, you will foster the enablement and support of advanced-node DRC, LVS, Antenna, and ESD signoff flows, working closely with EDA vendors, and internal design teams. You will own PV signoff methodology end to end, identify gap

Full-time

USD 119,800.00 - 234,700.00 per year

LVS jobs in South San Francisco, CA, USA