RTL jobs | Dice.com

California

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Today

Job Title: Senior RTL Engineer Location: Saratoga, CA (Onsite) Duration: Full-Time Job Description: Packet buffering, queuing, and scheduling: Work on micro architecture and design implementation of high-speed networking ASIC's, focusing on latency optimization and quality of service (QoS) support. Experience with on-chip memory subsystem and scheduling / arbitration design. Implementation and Testing: Implement designs on ASIC platforms, ensuring compliance with industry standards and perform

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Full-time

CPU Micro-Architect RTL Engineer

Austin, Texas

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > DSP Architecture and Design General Summary: Qualcomm is the world's largest fabless design company, delivering cutting-edge hardware, software, and services to nearly every mobile device maker and operator in the global wireless ecosystem. At the heart of Qualcomm's multi-tier mobile SoC, Server, IoT, and Automotive roadmap are our high-performance, multithreaded, low-power Hexagon cores. These cores pow

Full-time

USD 154,000.00 - 231,000.00 per year

RISCV CPU Systems Architecture/RTL Engineer - Senior Level

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: We are hiring talented engineers for RISCV CPU RTL development targeting high-performance, low-power devices. In this role, you will contribute to architecture and product definition and be responsible for microarchitecture and RTL execution of CPU system features. These include, but are not limited to: System architecture - configuration access protocols and ordering requi

Full-time

USD 198,700.00 - 298,100.00 per year

CPU RTL Methodology Engineer

Santa Clara, California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: We are seeking a highly skilled and versatile engineer who thrives at the intersection of RTL design and CAD automation. This role is ideal for someone who understands RTL workflows deeply and can build scalable automation solutions to streamline design and debug processes. You'll work closely with CPU design teams to support RTL development, triage issues, and enhance prod

Full-time

USD 198,700.00 - 298,100.00 per year

Physical design Engineer

Mountain View, California

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13d ago

Position 1 Physical Design Engineer Mountain View CA (onsite - Hybrid) Mode of hiring: Fulltime permanent Customer wants someone who is having some logical design experience along with PD experience. Having some RTL2PD flow skills such as CDC/RDC/VCLP is preferred. Having some exposure of logic design is also preferred. Canddiate doesn't have to do the logic design, but needs to review the synthesis/PNR report to analyze for the timing/LoL optimization Provides services in transforming the RTL d

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Full-time

$120,000 - $140,000

Physical Design Engineer

Palo Alto, California

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Today

JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivoltage (UPF)Power gating, clock gatingPerform physical verification and signoff:STA (Primetime)SI / CrosstalkIR drop & EM analysisWork on advanced nodes (7

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Contract

Depends on Experience

SoC / RTL Integration Engineer

Remote

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Today

This is Ganesh from DELLA INFOTECH INC. We have an outstanding opening for you for the opportunity below. Please check the job description and share your updated resume, if you are interested. Job Title : SoC / RTL Integration Engineer Location : Remote Good in understanding RTL Design and Digital concepts Subsystem or SoC integration Integration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc. SS integration using Verilog/system Verilog, synthesis, timing constraints,

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Contract

70 - 75

RTL Verification Engineer

Santa Clarita, California

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19d ago

RTL Verification Engineer System Verilog, UVM Good knowledge in AMBA,AX4,AHB IP/SS/SOC verification experience Test Env, test case development Regression debug, coverage analysis Good knowledge in One of the High speed IF protocol like PCIe6, DDR5, Ethernet or USB3 Experience in Synopsys/Cadance Tools usage

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Third Party, Contract

$55 - $57

DFT MBIST Staff Engineer

Remote

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Today

Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS

Contract

USD70.0/HOURLY - USD80.0/HOURLY

RTL Verification Engineer # 26-23383

Markham, Ontario

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6d ago

Duration: 8 months Description: As a Verification Engineer 5, you will play a key role in defining, developing, and executing advanced verification solutions for complex Display IP and SoC designs. You will work closely with architects, design engineers, software teams, and program managers to ensure first-pass silicon success and deliver high-quality products to market. The ideal candidate is passionate about verification methodologies, possesses strong expertise in System Verilog/UVM-based ver

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Contract

$80 - $100

RTL Verification Engineer # 26-21738

Ben Lomond, California

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6d ago

Duration: 12+ Months About the role:Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort.Be part of a team of design and verification engineers, working closely with other team members to understand and verify the functionality of a given design element within the context of the block, chip and overall system.Be responsible for carefully documenting and executing test plan(s) consisting of directed and constrained-ra

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Contract

$80 - $85

Physical Design Engineer

Hybrid in Sunnyvale, California

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Yesterday

We are hiring an experienced Physical Design Engineer to join a high-performing silicon engineering team supporting one of the world's leading technology organizations in Sunnyvale, CA. This is an exciting opportunity to work on cutting-edge ASIC/SoC designs and collaborate with talented engineers throughout the chip development lifecycle. Key Responsibilities Drive RTL synthesis and optimization to achieve performance, power, and area (PPA) goals Perform floorplanning for complex ASIC/SoC de

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Contract, Third Party

Depends on Experience

ASIC DESIGN LEAD / SENIOR CHIP DESIGN ENGINEER

Remote

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Today

ASIC CHIP LEAD ASIC Design Lead / Senior Chip Design Engineer What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tune RTL for power, performance and area. Design, imp

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Contract

100+

ASIC Design Lead / Senior Chip Design Engineer

Remote

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Today

Role:ASIC Design Lead / Senior Chip Design Engineer Location:REMOTE Duration: 12 months Contract Job Description What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tun

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Contract

95 - 105

Physical Design Engineer with Cadence Innovus

San Jose, California

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Today

Conduct EM/IR analysis.Strong experience with Cadence Innovus.Expertise in the complete Physical Design cycle from RTL to Tape-out.Strong TCL and/or PERL scripting skills.Develop and optimize Clock Tree Synthesis (CTS), including custom clock trees, insertion delay reduction, and skew balancing.Perform timing closure using various methodologies and strategies, including top-level STA.Collaborate closely with IC Design and RTL Engineering teams.

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Full-time

Depends on Experience

Physical Design Engineer

Irvine, California

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Today

Locations:San Jose, CA / San Diego, CA / Irvine, CARequired Skills Strong experience withCadence Innovus.Expertise in the complete Physical Design cycle fromRTL to Tape-out.Hands-on experience in:SynthesisStatic Timing Analysis (STA)Timing ClosurePlace & RouteClock Tree Synthesis (CTS)FloorplanningPhysical VerificationEM/IR AnalysisStrongTCL and/or PERL scriptingskills.

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Full-time

Depends on Experience

Physical Design Engineer

Palo Alto, California

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14d ago

Position: Physical Design Engineer Location : Palo Alto, CA (Full Onsite) Rate : 90-100/hr Client : HCL/Tesla Job ID : 166019 Number of Positions : 5 JD for PD: Exposure to TSMC 2NP/3NP is mustPerform endtoend physical design flow:FloorplanningPower planning (PG grid, IR)Placement & optimizationCTS (Clock Tree Synthesis)RoutingPostroute optimizationAchieve timing closure across all modes and cornersResolve DRC, LVS, ERC and signoff violationsHandle lowpower design techniques:MultiVt, Multivolta

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Contract

Depends on Experience

DFT (Design for Test) Engineer_SanJose, CA (Onsite)

San Jose, California

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Today

Design for Test (DFT) Engineer Location: San Jose, CA Duration: 12 + Months (Potential Extension) Interview Process: Virtual/Onsite Rate: Up to $130/hr on W2 (No Benefits) Job OverviewWe are seeking an experienced Design for Test (DFT) Engineer to support the development and validation of next-generation semiconductor products. The role involves close collaboration with Front-End Design and Physical Design teams to implement and optimize DFT solutions for advanced wireless and connectivity c

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Contract

100 - 130

DFT MBIST Staff Engineer

Remote

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8d ago

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Contract, Third Party

90 - 100

DFT (Design For Test) Lead - Remote Role

Remote

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Today

Role: ASIC DFT (Design for Test) LeadLocation: RemoteDuration: 12+ months (possibly extending longer based on project timelines)Candidate Responsibilities:Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debugResponsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with t

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Contract

Depends on Experience