RTL jobs in Ashville, OH

Remote

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Today

This is Ganesh from DELLA INFOTECH INC. We have an outstanding opening for you for the opportunity below. Please check the job description and share your updated resume, if you are interested. Job Title : SoC / RTL Integration Engineer Location : Remote Good in understanding RTL Design and Digital concepts Subsystem or SoC integration Integration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc. SS integration using Verilog/system Verilog, synthesis, timing constraints,

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Contract

70 - 75

ASIC DESIGN LEAD / SENIOR CHIP DESIGN ENGINEER

Remote

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Today

ASIC CHIP LEAD ASIC Design Lead / Senior Chip Design Engineer What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tune RTL for power, performance and area. Design, imp

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Contract

100+

ASIC Design Lead / Senior Chip Design Engineer

Remote

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Yesterday

Role:ASIC Design Lead / Senior Chip Design Engineer Location:REMOTE Duration: 12 months Contract Job Description What Youll Do Architecture and Chip Definition Lead ASIC architecture development from high-level requirements and block diagrams. Work with system architects to define chip functionality, interfaces and performance goals. Write detailed specifications for chip components and subsystems. RTL Design and Synthesis Develop RTL designs and run synthesis with Synopsys Design Compiler. Tun

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Contract

95 - 105

Integrated Circuit Backend/Physical Design Engineer

Columbus, Ohio

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Today

Battelle delivers when others can't. We conduct research and development, manage national laboratories, design and manufacture products and deliver critical services for our clients-whether they are a multi-national corporation, a small start-up or a government agency. We recognize and appreciate the value and contributions of individuals from a wide range of backgrounds and experiences and welcome all qualified individuals to apply. Job Summary Battelle's Advanced Microsystem Solutions Busin

Full-time

USD 86,400.00 - 123,100.00 per year

DFT MBIST Staff Engineer

Remote

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Today

Position Summary: We are looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS

Contract

USD70.0/HOURLY - USD80.0/HOURLY

DFT MBIST Staff Engineer

Remote

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8d ago

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Third Party, Contract

90 - 100

DFT (Design For Test) Lead - Remote Role

Remote

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Today

Role: ASIC DFT (Design for Test) LeadLocation: RemoteDuration: 12+ months (possibly extending longer based on project timelines)Candidate Responsibilities:Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debugResponsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with t

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Contract

Depends on Experience

Physical Design Engineer GPU / High-Performance SoC

Remote

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Today

Job Title: Physical Design Engineer GPU / High-Performance SoC Location: Mountain View, CA (Full Onsite) Openings: 2 Job Description We are looking for an experienced Physical Design Engineer with hands-on experience in advanced semiconductor process nodes, particularly TSMC 3nm and/or 2nm, for high-performance SoC, GPU, or similar complex chip designs. The ideal candidate will have strong end-to-end physical design experience, from netlist to GDSII, along with expertise in PPA optimization, tim

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Contract

$60 - $80

SOC/IP Integration Engineer (eInfochips Inc)

Remote or California

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Today

Position: SOC/IP Integration Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Good in understanding RTL Design and Digital conceptsSubsystem or SoC integrationIntegration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc.SS integration using verilog/system verilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, Lint, and RDC, register integration.Ensure customer satisfaction

Full-time

DV CAD Engineer

Remote or California

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Today

Company: Qualcomm Technologies, Inc. Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: As a CAD Engineer focusing on the methodology and support of RTL design verification, you will work with architecture, design, software and verification leads to develop technology critical to the development of our products. You will be involved from conception to final creation and every step along the way. Roles and Responsibilities Work with chip leads to understand the

Full-time

USD 186,700.00 - 280,100.00 per year

Principal Power Architect

Remote or California

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Today

Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute. As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications. Join us at Ampere and work alongside a passionate and growing team - we'd

Full-time

USD 182,000.00 - 273,000.00 per year

Distinguished Power Architect

Remote or California

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Today

Full-time

USD 279,500.00 - 419,500.00 per year

ASIC FPGA Engineer

Remote or Boise, Idaho

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Today

Basic Qualifications Education Requirements: Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 2 years of relevant experience; or Master's degree, plus 6 months of relevant experience. Clearance Requirements: Ability to obtain a Department of Defense Secret security clearance is required at time of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility req

Full-time

USD 103,585.00 - 110,000.00 per year

Senior FPGA Prototyping Engineer

Remote

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Today

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price - and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missi

Full-time

USD 120,000.00 - 225,000.00 per year

Design Verification Engineer

Remote

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Yesterday

Job SummaryWe are seeking a motivated Design Verification Engineer with 13 years of experience in digital design verification and semiconductor engineering. The candidate will work with RTL design and verification teams to develop testbenches, execute simulation-based verification, debug design issues, and validate the functionality and reliability of digital designs. The ideal candidate should have hands-on knowledge of Verilog, SystemVerilog, digital logic design, and verification methodologie

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Full-time

75000 - 100,000

Lead ASIC DFT Engineer

Remote

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Today

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues. The ideal candidate will have strong hands-on expertise in DFT fundamentals

Full-time

Asics Engineer

Remote

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Today

Requirements please see these key words of in the project description for the profile consideration. "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requir

Full-time

Lead ASIC DFT Staff Engineer

Remote

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8d ago

Required Skills & Qualifications: Strong hands-on experience in ASIC DFT with end-to-end ownership.Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.Experience with MBIST implementation and verific

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Third Party, Contract

90 - 100

DFT MBIST Staff Engineer

Remote

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15d ago

TechAGI Solutions is looking for a highly experienced Senior MBIST Contractor to join our SoC Design-for-Test (DFT) team. The role is focused on hands-on Memory BIST implementation using Synopsys MBIST (SMS). The ideal candidate is an independent contributor who can own the complete MBIST flow from insertion through verification, simulation, pattern generation, and Silicon bring-up with minimal supervision. Responsibilities: Perform MBIST insertion for complex SoC designs using Synopsys SMS.

Easy Apply

Full-time

100 - 110

Lead ASIC DFT Staff Engineer

Remote

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Today

Job Description: Key Skills : "SCAN, ATPG, MBIST, Timing Simulations, SDF, SDC , PSV, Diagnosys , Pattern Retargeting , Pattern porting, DRCs, TetraMax, DFTMax " Experience: 10+ years of hands-on experience in ASIC Design-for-Test (DFT) Role Summary: We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertio

Contract

USD70.0/HOURLY - USD80.0/HOURLY

RTL jobs in Ashville, OH 43103, USA